a
FEATURES
1 LSB Differential Linearity (max)
Guaranteed Monotonic Over Temperature Range
2 LSB Integral Linearity (max)
500 ns Settling Time
5 mA Full-Scale Output
TTL/CMOS Compatible
Low Power: 190 mW (typ)
Available in Die Form
APPLICATIONS
Communications
ATE
Data Acquisition Systems
High Resolution Displays
I
REF
REF GND
V
CC
AGND
V
EE
DGND
16-Bit High Speed
Current-Output DAC
DAC16
FUNCTIONAL BLOCK DIAGRAM
BUFFER
DAC16
C
COMP
DAC
I
OUT
DB0 (LSB)
DB15 (MSB)
GENERAL DESCRIPTION
0.1
The DAC16 is a 16-bit high speed current-output digital-to-
analog converter with a settling time of 500 ns. A unique com-
bination of low distortion, high signal-to-noise ratio, and high
speed make the DAC16 ideally suited to performing waveform
synthesis and modulation in communications, instrumentation,
and ATE systems. Input reference current is buffered, with full-
scale output current of 5 mA. The 16-bit parallel digital input
bus is TTL/CMOS compatible. Operating from +5 V and
–15 V supplies, the DAC16 consumes 190 mW (typ) and is
available in a 24-lead epoxy DIP, epoxy surface-mount small
outline (SOL), and in die form.
PERCENT OF FULL-SCALE – %
V
LOGIC
= +5V
TURNING OFF
V
LOGIC
= 0V
TURNING ON
0.01
I
FS
= 4mA
T
A
= 25 C
0.001
0
100
200
300
400
500
SETTLING TIME – ns
600
700
800
Figure 1. DAC16 Settling Time Accuracy vs. Percent of
Full Scale
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
DAC16–SPECIFICATIONS
(@ V
ELECTRICAL CHARACTERISTICS
Parameter
= +5.0 V, V
EE
= –15.0 V, I
REF
= 0.5 mA, C
COMP
= 47 F, T
A
= Full Operating Tem-
perature Range unless otherwise noted. See Note 1 for supply variations.)
CC
Conditions
Min
Typ
Max
Units
Integral Linearity “G”
Integral Linearity “G”
Differential Linearity “G”
Differential Linearity “G”
Integral Linearity “F”
Integral Linearity “F”
Differential Linearity “F”
Differential Linearity “F”
Zero Scale Error
Zero Scale Drift
Gain Error
Gain Drift
REFERENCE
2
Reference Input Current
OUTPUT CHARACTERISTICS
Output Current
Output Capacitance
Settling Time
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
Logic Input Current
Logic Input Current
Input Capacitance
SUPPLY CHARACTERISTICS
Power Supply Sensitivity
Positive Supply Current
Positive Supply Current
Negative Supply Current
Power Dissipation
INL
INL
DNL
DNL
INL
INL
DNL
DNL
ZSE
TC
ZSE
GE
TC
GE
I
REF
I
OUT
C
OUT
t
S
V
INH
V
INL
I
INH
I
INH
I
INL
C
IN
PSS
I
CC
I
CC
I
EE
P
DISS
T
A
= +25°C
T
A
= +25°C
T
A
= +25°C
T
A
= +25°C
–2
–4
–1
–1
–4
–6
–1
–1.5
±
1.2
±
1.6
±
0.5
±
0.7
±
1.4
±
2
±
0.5
±
0.6
0.025
5
+2
+4
+1
+1.5
+4
+6
+1.5
+2
1
±
0.225
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
ppm/°C
% FS
ppm/°C
µA
mA
pF
ns
V
V
µA
µA
µA
pF
ppm/V
mA
mA
mA
mW
Note 2
Note 2
0.003% of Full Scale
T
A
= +25°C
T
A
= +25°C
V
IN
= 5.0 V, DB0–DB10
V
IN
= 5.0 V, DB11–DB15
V
IN
= 0 V, DB0–DB15
350
2.8
10
500
2.4
625
5.0
0.8
7.5
100
1
8
V
CC
= 4.5 V to 5.5 V, V
EE
= –13 V to –17 V
All Bits HIGH
All Bits LOW
15
6
7.5
188
20
22
7.5
10
260
NOTES
1
All supplies can be varied
±
5% and operation is guaranteed. Device is tested with nominal supplies.
2
Operation is guaranteed over this reference range, but linearity is neither tested not guaranteed (see Figures 7 and 8).
Specifications subject to change without notice.
WAFER TEST LIMITS
(@ V
Parameter
CC
= +5.0 V, V
EE
= –15.0 V, I
REF
= 0.5 mA, C
COMP
= 47 F, T
A
= +25 C unless otherwise noted.)
Symbol
Conditions
DAC16G
Limit
Units
Integral Nonlinearity
Differential Nonlinearity
Zero Scale Error
Gain Error
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
Positive Supply Current
Negative Supply Current
Power Dissipation
INL
DNL
ZSE
GE
V
INH
V
INL
I
IN
I
CC
I
EE
P
DISS
±
3
±
1
±
1
±
12
2.4
0.8
75
20
10
250
LSB max
LSB max
LSB max
% FS max
V min
V max
µA
max
mA max
mA max
mW max
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
–2–
REV. B
DAC16
ABSOLUTE MAXIMUM RATINGS
(T
A
= +25°C unless otherwise noted)
CAUTION
V
CC
to V
EE
. . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +25.0 V
V
CC
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7.0 V
V
EE
to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –18.0 V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +0.3 V
REF GND to AGND . . . . . . . . . . . . . . . . . . . –0.3 V, +1.0 V
I
REF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 mA
Analog Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 8 mA
Digital Input Voltage to DGND . . . . . . . . . . . . . . . . . . .
≤V
CC
Operating Temperature Range
FP, FS . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
GS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Dice Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300°C
Package Type
θ
JA1
θ
JC
Units
1. Stresses above those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device. This is a
stress rating only and functional operation at or above this
specification is not implied. Exposure to the above maximum
rating conditions for extended periods may affect device
reliability.
2. Digital inputs and outputs are protected; however, perma-
nent damage may occur on unprotected units from high en-
ergy electrostatic fields. Keep units in conductive foam or
packaging at all times until ready to use. Use proper anti-
static handling procedures.
3. Remove power before inserting or removing units from their
sockets.
PIN CONFIGURATION
24-Lead DIP (P, S)
I
REF 1
DGND
2
V
CC 3
DB15 (MSB)
DB14
4
5
24
23
22
21
24-Lead Plastic DIP (P)
24-Lead Plastic SOL (S)
62
70
32
22
°C/W
°C/W
C
COMP
I
OUT
AGND
REF GND
V
EE
NOTE
1
θ
JA
is specified for worst case mounting conditions, i.e.,
θ
JA
is specified for
device in socket.
DAC16
20
DB13
6
DB12
7
TOP VIEW
19
DB0 (LSB)
(Not to Scale)
18
DB1
17
16
15
14
13
DICE CHARACTERISTICS
V
CC
DGND I
REF
C
COMP
I
OUT
AGND
DB11
8
DB10
9
DB9
REF GND
10
11
DB2
DB3
DB4
DB5
DB6
DB8
DB15 (MSB)
V
EE
DB14
DB0 (LSB)
DB7
12
PIN DESCRIPTION
Pin
(P, S) Name
DB13
DB12
DB11
DB1
DB2
DB10
DB3
DB9
DB8
DB7
DB6
DB5
DB4
Description
Die Size 0.129 x 0.153 inch, 19,737 sq. mils
(3.277 x 3.886 mm, 12.73 sq. mm)
The DAC16 Contains 330 Transistors.
Substrate is V
EE
Polarity.
1
2
3
4–19
20
21
22
23
24
I
REF
DGND
V
CC
DB15–DB0
V
EE
REF GND
AGND
I
OUT
C
COMP
Reference Current Input
Digital Ground
+5 V Digital Supply
16-Bit Digital Input Bus. DB15 is the MSB.
–15 V Analog Supply
Reference Current Return
Analog Ground/Output Reference
Current Output
Current Ladder Compensation
ORDERING GUIDE
Model
Grade DNL (max)
Temperature Ranges
Package Descriptions
Package Options
DAC16GS
DAC16FP
DAC16FS
DAC16GBC
±
1
±
2
±
2
±
1
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
+25°C
24-Lead SOL
24-Lead PDIP
24-Lead SOL
Die
R-24
N-24
R-24
REV. B
–3–
DAC16
+5V
10k
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
NC
minimizing the deleterious effects of digital feedthrough
while allowing the user to tailor the digital interface to
the speed requirements and bus configuration of the
application.
Equivalent Circuit Analysis
–15V
An equivalent circuit for static operation of the DAC16 is
illustrated in Figure 4. I
REF
is the current applied to the
DAC16 and is set externally to the device by V
REF
and
R
REF
. The output capacitance of the DAC16 is approxi-
mately 10 pF and is code independent. Its output resis-
tance R
O
is code dependent and is given by:
1
=
1
+
DB9
+
DB10
+
X
R
O
8
kΩ
288
kΩ
144
kΩ
72
kΩ
where
DB9
= State of Data Bit 9 = 0 or 1;
DB10
= State of Data Bit 10 = 0 or 1; and
X
= Decimal representation of the 5 MSBs (DB11–DB15)
= 0 to 31.
I
OUT
I
DAC
R
O
C
O
I
OUT
= 8 • I
REF
R
O
= SEE TEXT
C
O
= 10pF
65,535 Digital Code
65,536
Figure 2. Burn-In Diagram
OPERATION
Novel DAC Architecture
The DAC16 was designed with a compound DAC architecture
to achieve high accuracy, excellent linearity, and low transition
errors. As shown in Figure 3, the DAC’s five most-significant
bits utilize 31 identical segmented current sources to obtain
optimal high speed settling at major code transitions. The lower
nine bits utilize an inverted R-2R ladder network which is laser-
trimmed to ensure excellent differential nonlinearity. The middle
two bits (DB9 and DB10) arc binary-weighted and scaled from
the MSB segments. Note that the flow of output current is into
the DAC16—there is no signal inversion. As shown, the switches
for each current source are essentially diodes. It is for this rea-
son that the output voltage compliance of the DAC16 is limited
to a few millivolts. The DAC16 was designed to operate with an
operational amplifier configured as an I–V converter; therefore,
the DAC16’s output must be connected to the sum node of an
operational amplifier for proper operation. Exceeding the output
voltage compliance of the DAC16 will introduce linearity errors.
The reference current buffer assures full accuracy and fast set-
tling by controlling the MSB reference node. The 16-bit paral-
lel digital input is TTL/CMOS compatible and unbuffered,
Figure 4. Equivalent Circuit for the DAC16
Table I provides the relationship between the input digital
code and the output resistance of the DAC16.
Table I. DAC16 Output Resistance vs. Digital Code
Hex Digital Code
Scale
Output Resistance
FFFF
BFFF
7FFF
3FFF
0
Zero
1/4
1/2
3/4
Full – 1 LSB
8 kΩ
4.2 kΩ
2.9 kΩ
2.2 kΩ
1.8 kΩ
I
OUT
DB0 – DB8
AGND
DB11 – DB15
DB10
DB9
4k
18k
I
REF
8k
4k
8k
4k
4k
4k
DB0 – DB15
SWITCH DETAIL
SW0
+5V
FROM
SWITCH
DECODER
31 CURRENT SOURCES
125 A EACH
62.5 A 31.25 A
9 CURRENT SOURCES
15.63 A EACH
SW
SW
SW
SW
SW10
SW9
SW8
SW7
SW6
C
COMP
Figure 3. DAC16 Architecture
–4–
REV. B
Typical Performance Characteristics–DAC16
Digital Input Considerations
The threshold of the DAC16’s digital input circuitry is set at
1.4 V, independent of supply voltage. Hence, the digital inputs
can interface with any type of 5 V logic. Illustrated in Figure 5 is
the equivalent circuit of the digital inputs. Note that the indi-
vidual input capacitance is approximately 7 pF.
+5V
R2
75k
Q2
R1
20k
Q3
R3
28k
–15V
–0.7V
TO DAC
SWITCH
+0.7V
This input capacitance can be used in conjunction with an ex-
ternal R-C circuit for digital signal deskewing, if required. In
applications where some of the DAC16’s digital inputs are
not used, the recommended procedure to turn off one or more
inputs is to connect each input line to +5 V as shown in
Figure 6.
+5V
DBX
Q1
DAC16
DB0
DB1
Figure 5. Equivalent Circuit of a DAC16 Digital Input
Figure 6. Handling Unused DAC16 Digital Inputs
4
2.0
INTEGRAL NONLINEARITY – LSB
3
2
1
0
–1
–2
–3
–4
0.2
+INL
DIFFERENTIAL NONLINEARITY – LSB
V
CC
= +5V
V
EE
= –15V
T
A
= +25 C
1.0
V
CC
= +5V
V
EE
= –15V
T
A
= +25 C
ZERO SCALE – LSB
V
CC
= +5V
V
EE
= –15V
I
REF
= 0.5mA
1.5
1.0
0.5
0
–0.5
–DNL
–1.0
+DNL
0.8
0.6
0.4
–INL
0.2
–1.5
–2.0
0.2
0.3
0.4
0.5
0.6
REFERENCE CURRENT – mA
0.7
0
0.3
0.4
0.5
0.6
REFERENCE CURRENT – mA
0.7
0
20
40
60
–40 –20
TEMPERATURE – C
80
Figure 7. Integral Nonlinearity vs. I
REF
Figure 8. Differential Nonlinearity
vs. I
REF
Figure 9. Zero Scale Output vs.
Temperature
15
INTEGRAL NONLINEARITY – LSB
4
V
CC
= +5V
V
EE
= –15V
I
REF
= 0.5mA
DIFFERENTIAL NONLINEARITY – LSB
1.5
V
CC
= +5V
V
EE
= –15V
I
REF
= 0.5mA
+DNL
0
10
GAIN ERROR – LSB
+INL
2
1.0
5
0.5
–INL
0
0
–5
–2
–10
V
CC
= +5V
V
EE
= –15V
I
REF
= 0.5mA
–0.5
–DNL
–1.0
–15
–40 –20
0
20
40
60
TEMPERATURE – C
80
–4
–40 –20
0
20
40
60
TEMPERATURE – C
80
–1.5
–40 –20
0
20
40
60
TEMPERATURE – C
80
Figure 10. Gain Error vs.
Temperature
Figure 11. Integral Nonlinearity
vs. Temperature
Figure 12. Differential Nonlinearity
vs. Temperature
REV. B
–5–
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