16Mb: x16
IT SDRAM
SYNCHRONOUS
DRAM
FEATURES
• PC100 functionality
• Fully synchronous; all signals registered on
positive edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
1 Meg x 16 - 512K x 16 x 2 banks architecture with
11 row, 8 column addresses per bank
• Programmable burst lengths: 1, 2, 4, 8 or full page
• Auto Precharge Mode, includes CONCURRENT
AUTO PRECHARGE
• Self Refresh and Adaptable Auto Refresh Modes
- 32ms, 2,048-cycle refresh or
- 64ms, 2,048-cycle refresh or
- 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• Supports CAS latency of 1, 2 and 3
• Industrial temperature range: -40°C to +85°C
MT48LC1M16A1 SIT - 512K x 16 x 2 banks
INDUSTRIAL TEMPERATURE
For the latest data sheet, please refer to the Micron Web site:
www.micronsemi.com/datasheets/sdramds.html
PIN ASSIGNMENT (Top View)
50-Pin TSOP
V
DD
DQ0
DQ1
VssQ
DQ2
DQ3
V
DD
Q
DQ4
DQ5
VssQ
DQ6
DQ7
V
DD
Q
DQML
WE#
CAS#
RAS#
CS#
BA
A10
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
Vss
DQ15
DQ14
VssQ
DQ13
DQ12
V
DD
Q
DQ11
DQ10
VssQ
DQ9
DQ8
V
DD
Q
NC
DQMH
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
Vss
OPTIONS
• Configuration
1 Meg x 16 (512K x 16 x 2 banks)
• Plastic Package - OCPL*
50-pin TSOP (400 mil)
• Timing (Cycle Time)
6ns (166 MHz)
7ns (143 MHz)
8ns (125 MHz)
MARKING
1M16A1
Note:
The # symbol indicates signal is active LOW.
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
1 Meg x 16
512K x 16 x 2 banks
2K or 4K
2K (A0-A10)
2 (BA)
256 (A0-A7)
TG
-6
-7
-8A
16MB (X16) SDRAM PART NUMBER
PART NUMBER
MT48LC1M16A1TG SIT
ARCHITECTURE
1 Meg x 16
• Refresh
2K or 4K with Self Refresh Mode at 64ms
• Operating Temperature
-40°C to +85°C
Part Number Example:
S
IT
KEY TIMING PARAMETERS
SPEED
-6
-7
-8A
CLOCK
166 MHz
143 MHz
125 MHz
ACCESS TIME
CL = 3**
5.5ns
5.5ns
6ns
SETUP
2ns
2ns
2ns
HOLD
1ns
1ns
1ns
MT48LC1M16A1TG-7SIT
*Off-center parting line
**CL = CAS (READ) latency
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
16Mb: x16
IT SDRAM
GENERAL DESCRIPTION
The 16Mb SDRAM is a high-speed CMOS, dynamic
random-access memory containing 16,777,216 bits. It is
internally configured as a dual 512K x 16 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the 512K x
16-bit banks is organized as 2,048 rows by 256 columns by
16 bits. Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank and
row to be accessed (BA selects the bank, A0-A10 select the
row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column
location for the burst access.
The SDRAM provides for programmable READ or
WRITE burst lengths of 1, 2, 4 or 8 locations, or the full page,
with a burst terminate option. An AUTO PRECHARGE
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst sequence.
The 1 Meg x 16 SDRAM uses an internal pipelined
architecture to achieve high-speed operation. This archi-
tecture is compatible with the 2n rule of prefetch architec-
tures, but it also allows the column address to be changed
on every clock cycle to achieve a high-speed, fully random
access. Precharging one bank while accessing the alter-
nate bank will hide the PRECHARGE cycles and provide
seamless, high-speed, random-access operation.
The 1 Meg x 16 SDRAM is designed to operate in 3.3V,
low-power memory systems. An auto refresh mode is
provided, along with a power-saving, power-down mode.
All inputs and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operat-
ing performance, including the ability to synchronously
burst data at a high data rate with automatic column-
address generation, the ability to interleave between inter-
nal banks in order to hide precharge time, and the capability
to randomly change column addresses on each clock cycle
during a burst access.
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
16Mb: x16
IT SDRAM
TABLE OF CONTENTS
Functional Block Diagram - 1 Meg x 16 ................. 3
Pin Descriptions ........................................................ 4
Functional Description
........................................
Initialization ........................................................
Register Definitions .............................................
Mode Register ................................................
Burst Length ..............................................
Burst Type .................................................
CAS Latency ..............................................
Operating Mode .......................................
Write Burst Mode .....................................
Commands
..............................................................
Truth Table 1 (Commands and DQM Operation)
..............
Command Inhibit ...............................................
No Operation (NOP) ..........................................
Load Mode Register ............................................
Active ..................................................................
Read ..................................................................
Write ..................................................................
Precharge .............................................................
Auto Precharge ....................................................
Burst Terminate ...................................................
Auto Refresh ........................................................
Self Refresh ..........................................................
Operation
................................................................
Bank/Row Activation .........................................
Reads ..................................................................
Writes ..................................................................
Precharge .............................................................
Power-Down .......................................................
Clock Suspend ....................................................
Burst Read/Single Write ......................................
5
5
5
5
5
5
7
7
7
8
8
9
9
9
9
9
9
9
9
9
10
10
11
11
12
18
20
20
21
21
Concurrent Auto Precharge ................................
Truth Table 2 (CKE)
...................................................
Truth Table 3 (Current State, Same Bank)
.......................
Truth Table 4 (Current State, Different Bank)
...................
Absolute Maximum Ratings ....................................
DC Electrical Characteristics and
Operating Conditions ...........................................
I
DD
Specifications and Conditions ..........................
Capacitance ..............................................................
Timing Waveforms
Initialize and Load Mode Register ......................
Power-Down Mode ............................................
Clock Suspend Mode ..........................................
Auto Refresh Mode .............................................
Self Refresh Mode ...............................................
Reads
Read - Single Read .........................................
Read - Without Auto Precharge ....................
Read - With Auto Precharge ..........................
Alternating Bank Read Accesses ....................
Read - Full-Page Burst ....................................
Read - DQM Operation .................................
Writes
Write - Single Write .......................................
Write - Without Auto Precharge ...................
Write - With Auto Precharge .........................
Alternating Bank Write Accesses ...................
Write - Full-Page Burst ...................................
Write - DQM Operation ................................
22
24
25
27
29
29
29
30
AC Electrical Characteristics (Timing Table)
.... 30
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
16Mb: x16
IT SDRAM
FUNCTIONAL BLOCK DIAGRAM
1 Meg x 16 SDRAM
ROW
DECODER
11
ROW-
ADDRESS
LATCH
11
2,048
BANK0
MEMORY
ARRAY
(2,048 x 256 x 16)
CKE
CLK
DQML,
DQMH
WE#
CAS#
RAS#
COMMAND
DECODE
CS#
CONTROL
LOGIC
256 (x16)
SENSE AMPLIFIERS
I/O GATING
DQM MASK LOGIC
MODE REGISTER
256
16
DATA
OUTPUT
REGISTER
12
8
COLUMN-
ADDRESS BUFFER
BURST COUNTER
COLUMN-
ADDRESS LATCH
8
COLUMN
DECODER
16
16
DQ0-
DQ15
DATA
INPUT
8
REGISTER
256
A0-A10, BA
12
ADDRESS
REGISTER
REFRESH
CONTROLLER
SENSE AMPLIFIERS
I/O GATING
DQM MASK LOGIC
11
ROW-
ADDRESS
MUX
REFRESH
COUNTER
256 (x16)
11
ROW
DECODER
11
ROW-
ADDRESS
LATCH
11
2,048
BANK1
MEMORY
ARRAY
(2,048 x 256 x 16)
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
16Mb: x16
IT SDRAM
PIN DESCRIPTIONS
PIN NUMBERS
35
SYMBOL
CLK
TYPE
DESCRIPTION
Input Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.
Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK
signal. Deactivating the clock provides PRECHARGE POWER-DOWN
and SELF REFRESH operations (all banks idle), ACTIVE POWER-DOWN
(row ACTIVE in either bank) or CLOCK SUSPEND operation (burst/access
in progress). CKE is synchronous except after the device enters power-
down and self refresh modes, where CKE becomes asynchronous until
after exiting the same mode. The input buffers, including CLK, are
disabled during power-down and self refresh modes, providing low
standby power. CKE may be tied HIGH.
Input Chip Select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS# is
registered HIGH. CS# provides for external bank selection on systems
with multiple banks. CS# is considered part of the command code.
Input Command Inputs: RAS#, CAS# and WE# (along with CS#) define the
command being entered.
Input
Input/Output Mask: DQM is an input mask signal for write accesses and an
output enable signal for read accesses. Input data is masked when
DQM is sampled HIGH during a WRITE cycle. The output buffers are
placed in a High-Z state (two-clock latency) when DQM is sampled
HIGH during a READ cycle. DQML corresponds to DQ0-DQ7; DQMH
corresponds to DQ8-DQ15.
DQML and DQMH are considered same state when referenced as DQM.
34
CKE
18
CS#
15, 16, 17
14, 36
WE#, CAS#,
RAS#
DQML,
DQMH
19
BA
Input Bank Address Inputs: BA defines to which bank the ACTIVE, READ,
WRITE or PRECHARGE command is being applied. BA is also used to
program the twelfth bit of the Mode Register.
Input Address Inputs: A0-A10 are sampled during the ACTIVE command
(row-address A0-A10) and READ/WRITE command (column-address A0-
A7, with A10 defining AUTO PRECHARGE) to select one location out of
the 512K available in the respective bank. A10 is sampled during a
PRECHARGE command to determine if all banks are to be precharged
(A10 HIGH). The address inputs also provide the op-code during a
LOAD MODE REGISTER command.
Input/ Data I/Os: Data bus.
Output
–
No Connect: These pins should be left unconnected.
21-24, 27-32, 20
A0-A10
2, 3, 5, 6, 8, 9,
11, 12, 39, 40, 42,
43, 45, 46, 48, 49
33, 37
7, 13, 38, 44
4, 10, 41, 47
1, 25
26, 50
DQ0-
DQ15
NC
V
DD
Q
V
SS
Q
V
DD
V
SS
Supply DQ Power: Provide isolated power to DQs for improved noise immu-
nity.
Supply DQ Ground: Provide isolated ground to DQs for improved noise
immunity.
Supply Power Supply: +3.3V ±0.3V.
Supply Ground.
16Mb: x16 IT SDRAM
16MSDRAMx16IT.p65 – Rev. 5/99
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
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