Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
1
FEATURES
TDA10085HT
•
DSS and DVB-S compliant single chip demodulator and
forward error correction
•
Dual 6-bit Analog-to-Digital Converter (ADC) on-chip
•
PLL that allows using a low-cost crystal
(typically 4 MHz)
•
DiSEqC 1.X from 1 to 8 byte-long sequences with
modulated or unmodulated output
•
DSS dish control
•
Digital cancellation of ADC offset
•
Simultaneous parallel and serial output interfaces
•
Variable rate BPSK/QPSK coherent demodulator
•
Modulation rate variable from 1 to 49 Mbauds
•
Automatic gain control output
•
Digital symbol timing recovery:
– Acquisition range up to 960 ppm
•
Carrier offset cancellation up to one half of the sampling
frequency
•
Digital carrier recovery:
– Acquisition range up to 12% of the symbol rate
•
Half-Nyquist filters: roll-off = 0.35 for DVB and
0.2 for DSS
•
Interpolating and anti-aliasing filters to handle variable
symbol rates
•
Channel quality estimation
•
Spectral inversion ambiguity resolution
•
Viterbi decoder:
– Supported rates from 1/2 to 8/9
– Constraint length K = 7 with G1 = 171
8
and
G2 = 133
8
– Viterbi output BER measurement
– Automatic code rate search within
1
/
2
,
2
/
3
and
6
/
7
in
DSS mode
– Automatic code rate search within
1
/
2
,
2
/
3
,
3
/
4
,
5
/
6
and
7
/
8
in DVB-S mode
•
Convolutional de-interleaver and Reed Solomon
decoder according to DVB and DSS specifications
•
Automatic frame synchronization
•
Selectable DVB-S descrambling
•
I
2
C-bus interface
•
64-pin TQFP package
•
CMOS technology (0.2
µm,
1.8 V to 3.3 V).
2
APPLICATIONS
•
DVB-S receivers (ETS 300-421)
•
DSS receivers.
3
GENERAL DESCRIPTION
The TDA10085 is a single-chip channel receiver for
satellite television reception matching both DSS and
DVB-S standards. The device contains a dual 6-bit flash
ADC, variable rate BPSK/QPSK coherent demodulator
and forward error correction functions. The ADC interfaces
directly with I and Q analog baseband signals.
After analog-to-digital conversion, the TDA10085
implements a bank of cascadable filters as well as
anti-alias and half-Nyquist filters. An analog AGC signal is
generated using an amplitude estimation function. The
TDA10085 performs clock recovery at twice the baud rate
and achieves coherent demodulation without any
feedback to the local oscillator. Forward error correction is
built around two error-correcting codes: a Reed-Solomon
(outer code) and a Viterbi decoder (inner code). The
Reed-Solomon decoder corrects up to 8 erroneous bytes
among the N (204) bytes of one data packet.
A convolutional de-interleaver is located between the
Viterbi output and the Reed-Solomon decoder input. The
de-interleaver and Reed-Solomon decoder are
automatically synchronized according to a frame
synchronization algorithm that uses the sync pattern
present in each packet. The TDA10085 is controlled via an
I
2
C-bus interface. The circuit operates at sampling
frequencies up to 100 MHz, can process variable
modulation rates and achieves transmission rates up to
45 Mbaud. Furthermore, for dish control applications,
hardware supports DiSEqc 1.x with control access via the
I
2
C-bus.
An interrupt line that can be programmed to activate on
events or on timing information is provided.
Designed in 20 micron CMOS technology and housed in a
TQFP64 package, the TDA10085 operates over the
commercial temperature range.
2001 Aug 31
3
Philips Semiconductors
Product specification
Single chip DVB-S/DSS channel receiver
6
PINNING
SYMBOL
XIN
XOUT
VDDI
PLLVCC
PLLGND
DGND
DVCC
VDDI
VSSI
VDD3
AVS
VIN2
VREFN
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
TYPE
I
I
supply
supply
ground
ground
supply
supply
ground
supply
ground
I
O
DESCRIPTION
TDA10085HT
crystal oscillator input and output pins; in a typical application, a
fundamental oscillator crystal is connected between pins XIN and
XOUT; see note 1
digital core supply voltage (typically 1.8 V)
analog supply voltage for the PLL (typically 3.3 V)
analog ground for the PLL
digital PLL core ground voltage; see note 2
digital PLL core supply voltage (typically 1.8 V)
digital ADC supply voltage (typically 1.8 V)
digital ADC ground voltage; see note 2
analog ADC supply voltage (typically 3.3 V)
analog ground voltage
analog signal input for channel Q; see note 1
negative analog voltage reference output (typically 1.25 V); a
decoupling capacitor (typically 0.1
µF)
must be placed as close as
possible between VREFN and GND
positive analog voltage reference output (typically 2 V); a decoupling
capacitor (typically 0.1
µF)
must be placed as closed as possible
between VREFP and GND
analog signal input for channel I; see note 1
analog supply voltage (typically 3.3 V); a 0.1
µF
decoupling capacitor
must be placed between AVD and AVS
SADDR0 input signal is the LSB of the I
2
C-bus address of the
TDA10085; other bits of the address are set internally to 000111,
therefore the complete I
2
C-bus address is (MSB to LSB):
0, 0, 0, 1, 1, 1 plus the SADDR0 bit; see note 1
test input; must be connected to ground for normal operation; see
note 1
enable serial interface input; when HIGH, the serial transport stream
is present on the boundary scan pins (TRST, TDO, TCK, TDI
and TMS); when LOW, the boundary scan pins are available; note 1
input to select the I
2
C-bus internal system clock frequency (depends
on the crystal frequency); internal I
2
C-bus clock is XIN when
IICDIV = 0 and XIN/4 if IICDIV = 1; see note 1
control line output 1; this pin function is directly programmable
through the I
2
C-bus interface; default value is logic 1; open-drain
output requiring an external pull-up resistor to 3.3 V or to 5 V
control line output 2; this pin function is directly programmable
through the I
2
C-bus interface; default value is logic 1; open-drain
output requiring an external pull-up resistor to 3.3 V or to 5 V
digital ground voltage; see note 2
digital 5 V supply voltage; required for the 5 V tolerance of inputs
digital core ground voltage; see note 2
VREFP
14
O
VIN1
AVD
SADDR0
15
16
17
I
supply
I
TMD
ENSERI
18
19
I
I
IICDIV
20
I
CTRL1
21
OD
CTRL2
22
OD
VSSE
VDDE5
VSSI
23
24
25
ground
supply
ground
2001 Aug 31
5
FPGA/CPLD
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