CS493302-IL datasheet, PDF - EEWORLD Datasheet

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CS493302-IL: Descriptionmulti-standard audio decoder family; CategoryOther integrated circuit (IC) Consumption circuit; File Size1MB，86 Pages; ManufacturerCirrus Logic; Websitehttp://www.cirrus.com

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CS493302-IL Overview

multi-standard audio decoder family

CS493302-IL Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Cirrus Logic
Parts packaging code	LCC
package instruction	QCCJ, LDCC44,.7SQ
Contacts	44
Reach Compliance Code	unknown
Commercial integrated circuit types	CONSUMER CIRCUIT
JESD-30 code	S-PQCC-J44
JESD-609 code	e0
length	16.5862 mm
Number of functions	1
Number of terminals	44
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC44,.7SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	225
power supply	2.5 V
Certification status	Not Qualified
Maximum seat height	4.572 mm
Maximum slew rate	314 mA
Maximum supply voltage (Vsup)	2.63 V
Minimum supply voltage (Vsup)	2.37 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	16.5862 mm
Base Number Matches	1

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CS49300 Family DSP

Multi-Standard Audio Decoder Family

Features

CS4930X: DVD Audio Sub-family

—

PES Layer decode for A/V sync

DVD Audio Pack Layer Support

Meridian Lossless Packing Specification (MLP)™

Dolby Digital™, Dolby Pro Logic II™

MPEG-2, Advanced Audio Coding Algorithm (AAC)

MPEG Multichannel

DTS Digital Surround™, DTS-ES Extended Surround™

PES Layer decode for A/V sync

Dolby Digital

MPEG-2, Advanced Audio Coding Algorithm (AAC)

MPEG-1 (Layers 1, 2, 3) Stereo

MPEG-2 (Layers 2, 3) Stereo

Dolby Digital, Dolby Pro Logic II

DTS & DTS-ES decoding with integrated DTS tables

Cirrus Original Surround 5.1 PCM Enhancement

MPEG-2, Advanced Audio Coding Algorithm (AAC)

MPEG Multichannel

MP3 (MPEG-1, Layer 3)

Description

The CS493XX is a family of multichannel audio decoders

intended to supersede the CS4923/4/5/6/7/8/9 family as the

leader of audio decoding in both the DVD, broadcast and

receiver markets. The family will be split into parts tailored for

each of these distinct market segments.

For the DVD market, parts will be offered which support Meridian

Lossless Packing (MLP), Dolby Digital, Dolby Pro Logic II,

MPEG Multichannel, DTS Digital Surround, DTS-ES, AAC, and

subsets thereof. For the receiver market, parts will be offered

which support Dolby Digital, Dolby Pro Logic II, MPEG

Multichannel, DTS Digital Surround, DTS-ES, AAC, and various

virtualizers and PCM enhancement algorithms such as HDCD

DTS Neo:6

, LOGIC7

, and SRS Circle Surround II

. For the

broadcast market, parts will be offered which support Dolby

Digital, AAC, MPEG-1, Layers 1,2 and 3, MPEG-2, Layers 2 and

Under the Crystal brand, Cirrus Logic is the only single supplier

of high-performance 24-bit multi-standard audio DSP decoders,

DSP firmware, and high-resolution data converters. This

combination of DSPs, system firmware, and data converters

simplify rapid creation of world-class high-fidelity digital audio

products for the Internet age.

CS4931X: Broadcast Sub-family

CS4932X: AVR Sub-family

— THX

Surround EX™ and THX

Ultra2 Cinema

— General Purpose AVR and Broadcast Audio Decoder

(MPEG Multichannel, MPEG Stereo, MP3, C.O.S.)

— Car Audio

CS49330: General Purpose Audio DSP

Ordering Information:

See

page 85

APPLICATION

CS49300

CS49310

CS49311

CS49312

CS49325

CS49326

CS49329

CS49330

DVD Audio

Broadcast

AVR

Car Audio DSP

General Purpose

Post-Processor

CORE DECODER FUNCTIONALITY

MLP, AC-3, AAC, DTS, MPEG 5.1, MP3, etc.

AAC, AC-3, MPEG Stereo, MP3, etc.

AAC, MPEG Stereo, MP3, etc.

AC-3, MPEG Stereo, MP3, etc.

AC-3, COS, MPEG 5.1, MP3, etc.

AC-3, DTS, COS, MPEG 5.1, MP3, etc.

AC-3, AAC, DTS, MPEG 5.1, MP3, etc.

Car Audio Code

MPEG 5.1, MPEG Stereo, MP3, C.O.S., etc

DPP,

THX Surround EX, THX Ultra2 Cinema

Features are a super-set of the CS4923/4/5/6/7/8/9

— 8 channel output, including dual zone output capability

— Dynamic Channel Remapability

— Supports up to 192 kHz Fs @ 24-bit throughput

— Increased memory/MIPs

— SRAM Interface for increased delay and buffer capability

— Dual-Precision Bass Manager

— Enhance your system functionality via firmware

upgrades through the Crystal Ware

Software

Licensing Program

RESET

CMPDAT,

SDATAN2

CMPCLK,

SCLKN2

CMPREQ,

LRCLKN2

SCLKN1,

STCCLK2

LRCLKN1

SDATAN1

CLKIN

CLKSEL

RD,

WR,

SCDIO,

DATA7:0,

R/W,

DS,

SCDOUT,

EMOE, EMWR,

PSEL,

ABOOT,

EMAD7:0,

A0,

A1,

GPIO7:0

GPIO11 GPIO10 GPIO9 SCCLK SCDIN

INTREQ

EXTMEM,

GPIO8

Compressed

Data Input

Interface

Parallel or Serial Host Interface

Framer

Shifter

Input

Buffer

Controller

24-Bit

DSP Processing

RAM

Program Data

Memory Memory

ROM

Program Data

Memory Memory

STC

MCLK

SCLK

Output

Formatter

LRCLK

AUDATA[2.0]

Digital

Audio

Input

Interface

PLL

Clock Manager

FILT2 FILT1

RAM Input

Buffer

RAM

Output

Buffer

XMT958/AUDATA3

VA AGND

DGND[3:1]

VD[3:1]

Preliminary Product Information

P.O. Box 17847, Austin, Texas 78760

(512) 445 7222 FAX: (512) 445 7581

http://www.cirrus.com

This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.



Cirrus Logic, Inc. 2002

MAR ‘02

DS339PP4

CS49300 Family DSP

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ................................................................. 6

1.1 Absolute Maximum Ratings ........................................................................................ 6

1.2 Recommended Operating Conditions ......................................................................... 6

1.3 Digital D.C. Characteristics ......................................................................................... 6

1.4 Power Supply Characteristics ..................................................................................... 6

1.5 Switching Characteristics — RESET ........................................................................ 7

1.6 Switching Characteristics — CLKIN ............................................................................ 7

1.7 Switching Characteristics — Intel

Host Mode ........................................................... 8

1.8 Switching Characteristics — Motorola

Host Mode .................................................. 10

1.9 Switching Characteristics — SP

Control Port .......................................................... 12

1.10 Switching Characteristics — I

Control Port ....................................................... 14

1.11 Switching Characteristics — Digital Audio Input ..................................................... 16

1.12 Switching Characteristics — CMPDAT, CMPCLK .................................................. 18

1.13 Switching Characteristics — Parallel Data Input ..................................................... 18

1.14 Switching Characteristics — Digital Audio Output ................................................... 19

2. FAMILY OVERVIEW ....................................................................................................... 21

2.1 Multichannel Decoder Family of Parts ...................................................................... 21

3. TYPICAL CONNECTION DIAGRAMS ........................................................................... 24

3.1 Multiplexed Pins ........................................................................................................ 24

3.2 Termination Requirements ........................................................................................ 25

3.3 Phase Locked Loop Filter ......................................................................................... 25

4. POWER ........................................................................................................................... 25

4.1 Decoupling ................................................................................................................ 25

4.2 Analog Power Conditioning ....................................................................................... 25

Contacting Cirrus Logic Support

For a com plete listing of D irect S ales, D istributor, and S ales R epresentative contacts, visit the Cirrus Logic w eb site at:

http://www.cirrus.com/corporate/contacts

Dolby Digital, AC-3, Dolby Pro Logic, Dolby Pro Logic II, Dolby Surround, Surround EX, Virtual Dolby Digital, MLP and the “AAC” logo are trademarks

and the “Dolby Digital” logo, “Dolby Digital with Pro Logic II” logo, “Dolby” and the double-”D” symbol are registered trademarks of Dolby Laboratories

Licensing Corporation. DTS, DTS Digital Surround, DTS-ES Extended Surround, DTS Neo:6, and DTS Virtual 5.1 are trademarks and the “DTS”,

“DTS-ES”, “DTS Virtual 5.1” logos are registered trademarks of the Digital Theater Systems Corporation. The “MPEG Logo” is a registered trademark

of Philips Electronics N.V. Home THX Cinema and THX are registered trademarks of Lucasfilm Ltd. Surround EX is a jointly developed technology

of THX and Dolby Labs, Inc. AAC (Advanced Audio Coding) is an “MPEG-2-standard-based” digital audio compression algorithm (offering up 5.1

discrete decoded channels for this implementation) collaboratively developed by AT&T, the Fraunhofer Institute, Dolby Laboratories, and the Sony

Corporation. In regards to the MP3 capable functionality of the CS49300 Family DSP (via downloading of mp3_493xxx_vv.ld and mp3e_493xxx_vv.ld

application codes) the following statements are applicable: “Supply of this product conveys a license for personal, private and non-commercial use.

MPEG Layer-3 audio decoding technology licensed from Fraunhofer IIS and THOMSON Multimedia.” MLP and Meridian Lossless Packing are

registered trademarks of Meridian Audio Ltd. Harman VMAx is a registered trademark of Harman International. The LOGIC7 logo and LOGIC7 are

registered trademarks of Lexicon. SRS Circle Surround, and SRS TruSurround are trademarks of SRS Labs, Inc. The HDCD logo, HDCD, High

Definition Compatible Digital and Pacific Microsonics are either registered trademarks or trademarks of Pacific Microsonics, Inc. in the United States

and/or other countries. HDCD technology provided under license from Pacific Microsonics, Inc. This product’s software is covered by one or more of

the following in the United States: 5,479,168; 5,638,074; 5,640,161; 5,872,531; 5,808,574; 5,838,274; 5,854,600; 5,864,311; and in Australia:

669114; with other patents pending. Intel is a registered trademark of Intel Corporation. Motorola is a registered trademark of Motorola, Inc. I

C is a

registered trademark of Philips Semiconductor. Purchase of I

C Components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies

conveys a license under the Philips I

C Patent Rights to use those components in a standard I

C system. The “Cirrus Logic Logo” is a registered

trademark of Cirrus Logic, Inc. All other names are trademarks, registered trademarks, or service marks of their respective companies.

Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance

product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to

ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is

provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information,

nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents,

copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any

form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus

Logic web site or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a

retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent

of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or

service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can

be found at http://www.cirrus.com.

DS339PP4

CS49300 Family DSP

4.3 Ground ...................................................................................................................... 32

4.4 Pads ......................................................................................................................... 32

5. CLOCKING ..................................................................................................................... 32

6. CONTROL ...................................................................................................................... 32

6.1 Serial Communication .............................................................................................. 33

6.1.1 SPI Communication ...................................................................................... 33

6.1.2 I

C Communication ...................................................................................... 35

6.1.3 INTREQ Behavior: A Special Case .............................................................. 39

6.2 Parallel Host Communication ................................................................................... 41

6.2.1 Intel Parallel Host Communication Mode ..................................................... 43

6.2.2 Motorola Parallel Host Communication Mode .............................................. 45

6.2.3 Procedures for Parallel Host Mode Communication .................................... 46

7. EXTERNAL MEMORY .................................................................................................... 48

7.1 Non-Paged Memory ................................................................................................. 49

7.2 Paged Memory ........................................................................................................ 49

8. BOOT PROCEDURE & RESET ..................................................................................... 52

8.1 Host Boot .................................................................................................................. 52

8.1.1 Serial Download Sequence .......................................................................... 52

8.1.2 Parallel Download Sequence ....................................................................... 55

8.2 Autoboot ................................................................................................................... 56

8.2.1 Autoboot INTREQ Behavior ......................................................................... 57

8.3 Decreasing Autoboot Times Using GFABT Codes (Fast Autoboot) ......................... 59

8.3.1 Design Considerations when using GFABT Codes ...................................... 61

8.4 Internal Boot ............................................................................................................. 61

8.5 Application Failure Boot Message ............................................................................ 61

8.6 Resetting the CS493XX ............................................................................................ 61

8.7 External Memory Examples ...................................................................................... 63

8.7.1 Non-Paged Autoboot Memory ...................................................................... 63

8.7.2 32 Kilobyte Paged Autoboot Memory ........................................................... 64

8.8 CDB49300-MEMA.0 ................................................................................................. 65

9. HARDWARE CONFIGURATION ................................................................................... 67

10.DIGITAL INPUT & OUTPUT ........................................................................................... 67

10.1 Digital Audio Formats .............................................................................................. 67

10.1.1 I

S .............................................................................................................. 67

10.1.2 Left Justified ............................................................................................... 67

10.1.3 Multichannel ............................................................................................... 67

10.2 Digital Audio Input Port ........................................................................................... 68

10.3 Compressed Data Input Port ................................................................................... 69

10.4 Byte Wide Digital Audio Data Input ......................................................................... 69

10.4.1 Parallel Delivery with Parallel Control ........................................................ 69

10.4.2 Parallel Delivery with Serial Control ........................................................... 70

10.5 Digital Audio Output Port ......................................................................................... 70

10.5.1 IEC60958 Output ........................................................................................ 71

11.HARDWARE CONFIGURATION ................................................................................... 72

11.1 Address Checking ................................................................................................... 72

11.2 Input Data Hardware Configuration ........................................................................ 72

11.2.1 Input Configuration Considerations ......................................................... 75

11.3 Output Data Hardware Configuration ...................................................................... 76

11.3.1 Output Configuration Considerations ........................................................ 78

11.4 Creating Hardware Configuration Messages .......................................................... 78

DS339PP4

CS49300 Family DSP

12.PIN DESCRIPTIONS ....................................................................................................... 80

13.ORDERING INFORMATION............................................................................................ 85

14.PACKAGE DIMENSIONS ............................................................................................... 85

LIST OF FIGURES

Figure 1. RESET Timing ..................................................................................................................... 7

Figure 2. CLKIN with CLKSEL = VSS = PLL Enable .......................................................................... 7

Figure 3. Intel

Parallel Host Mode Read Cycle ................................................................................. 9

Figure 4. Intel

Parallel Host Mode Write Cycle ................................................................................. 9

Figure 5. Motorola

Parallel Host Mode Read Cycle ........................................................................ 11

Figure 6. Motorola

Parallel Host Mode Write Cycle ........................................................................ 11

Figure 7. SPI Control Port Timing ..................................................................................................... 13

Figure 8. I2C

Control Port Timing ................................................................................................... 15

Figure 9. Digital Audio Input Data, Master and Slave Clock Timing ................................................. 17

Figure 10. Serial Compressed Data Timing ...................................................................................... 18

Figure 11. Parallel Data Timing (when not in a parallel control mode) ............................................. 18

Figure 12. Digital Audio Output Data, Input and Output Clock Timing ............................................. 20

Figure 13. I

Control ..................................................................................................................... 26

Figure 14. I

Control with External Memory ................................................................................. 27

Figure 15. SPI Control ...................................................................................................................... 28

Figure 16. SPI Control with External Memory ................................................................................... 29

Figure 17. Intel

Parallel Control Mode ............................................................................................ 30

Figure 18. Motorola

Parallel Control Mode ..................................................................................... 31

Figure 19. SPI Write Flow Diagram .................................................................................................. 33

Figure 20. SPI Read Flow Diagram .................................................................................................. 34

Figure 21. SPI Timing ....................................................................................................................... 36

Figure 22. I2C® Write Flow Diagram ................................................................................................ 37

Figure 23. I2C® Read Flow Diagram ................................................................................................ 38

Figure 24. I2C® Timing ..................................................................................................................... 40

Figure 24. Intel Mode, One-Byte Write Flow Diagram ...................................................................... 44

Figure 25. Intel Mode, One-Byte Read Flow Diagram ...................................................................... 44

Figure 26. Motorola Mode, One-Byte Write Flow Diagram ............................................................... 45

Figure 27. Motorola Mode, One-Byte Read Flow Diagram ............................................................... 46

Figure 28. Typical Parallel Host Mode Control Write Sequence Flow Diagram ............................... 47

Figure 29. Typical Parallel Host Mode Control Read Sequence Flow Diagram ............................... 48

Figure 30. External Memory Interface .............................................................................................. 51

Figure 31. External Memory Read (16-bit address) ......................................................................... 51

Figure 32. External Memory Write (16-bit address) .......................................................................... 51

Figure 33. Typical Serial Boot and Download Procedure ................................................................. 53

Figure 34. Typical Parallel Boot and Download Procedure .............................................................. 54

Figure 35. Autoboot Timing Diagram ................................................................................................ 56

Figure 37. Autoboot INTREQ Behavior ............................................................................................ 57

Figure 36. Autoboot Sequence ......................................................................................................... 58

DS339PP4

CS49300 Family DSP

Figure 38. Fast Autoboot Sequence Using GFABT Codes ...............................................................60

Figure 39. Performing a Reset ..........................................................................................................62

Figure 40. Non-Paged Memory .........................................................................................................64

Figure 41. Example Contents of a Paged 32 Kilobytes External Memory (Total 256 Kilobytes) .......64

Figure 42. CDB49300-MEMA.0 Daughter Card for the CDB4923/30-REV-A.0 ................................66

Figure 43. I

S Format ........................................................................................................................68

Figure 44. Left Justified Format (Rising Edge Valid SCLK) ...............................................................68

Figure 45. Multichannel Format .........................................................................................................68

LIST OF TABLES

Table 1. PLL Filter Component Values .............................................................................................. 25

Table 2. Host Modes .......................................................................................................................... 32

Table 3. SPI Communication Signals................................................................................................. 33

Table 4. I

C® Communication Signals ............................................................................................. 35

Table 5. Parallel Input/Output Registers ............................................................................................ 42

Table 6. Intel Mode Communication Signals...................................................................................... 43

Table 7. Motorola Mode Communication Signals .............................................................................. 45

Table 8. Memory Interface Pins ......................................................................................................... 49

Table 9. Boot Write Messages ........................................................................................................... 52

Table 10. Boot Read Messages......................................................................................................... 52

Table 11. Reduced Autoboot Times using GFABT8.LD, GFABT6.LD, and GFABT4.LD

on a CS493264-CL Rev. G DSP........................................................................................................ 59

Table 12. Memory Requirements for Example 5.1, 6.1 and 7.1 Channel Systems ........................... 63

Table 13. Digital Audio Input Port ...................................................................................................... 68

Table 14. Compressed Data Input Port.............................................................................................. 69

Table 15. Digital Audio Output Port.................................................................................................... 70

Table 16. MCLK/SCLK Master Mode Ratios...................................................................................... 71

Table 17. Output Channel Mapping ................................................................................................... 71

Table 18. Input Data Type Configuration

(Input Parameter A)............................................................................................................................ 73

Table 19. Input Data Format Configuration

(Input Parameter B)............................................................................................................................ 73

Table 20. Input SCLK Polarity Configuration

(Input Parameter C) ........................................................................................................................... 75

Table 21. Input FIFO Setup Configuration

(Input Parameter D) ........................................................................................................................... 75

Table 22. Output Clock Configuration

(Parameter A)..................................................................................................................................... 76

Table 23. Output Data Format Configuration

(Parameter B)..................................................................................................................................... 76

Table 24. Output MCLK Configuration

(Parameter C) .................................................................................................................................... 77

Table 25. Output SCLK Configuration

(Parameter D) .................................................................................................................................... 77

Table 26. Output SCLK Polarity Configuration

(Parameter E)..................................................................................................................................... 77

Table 27. Example Values to be Sent to CS493XX After Download or Soft Reset ........................... 79

DS339PP4

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