CS4205 datasheet, PDF - EEWORLD Datasheet

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CS4205: Descriptioncrystalclear audio codec 97 with portable computing; File Size877KB，80 Pages; ManufacturerCirrus Logic; Websitehttp://www.cirrus.com

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CS4205 Overview

crystalclear audio codec 97 with portable computing

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CS4205

CrystalClear



Audio Codec ’97 for Portable Computing

Features

Integrated

Three

Asynchronous I

S Input Port

(ZV Port)

Integrated High-Performance Microphone

Pre-Amplifier

Integrated Digital Effects Processing for Bass

and Treble Response

Digital Docking Including an I

S Output, 3

Synchronous I

S Inputs

Performance Oriented Digital Mixer

SRS



3D Stereo Enhancement

On-chip PLL for use with External Clock

Sources

Dedicated Microphone Analog-to-Digital

Converter

Sample Rate Converters

S/PDIF Digital Audio Output

AC ’97 2.1 Compliant

PC Beep Bypass

20-bit Stereo Digital-to-Analog Converters

18-bit Stereo Analog-to-Digital Converters

Analog Line-level Stereo Inputs for

LINE IN, VIDEO, and AUX

High Quality Pseudo-Differential CD Input

Extensive Power Management Support

Meets or Exceeds the Microsoft



PC 99 and

PC 2001 Audio Performance Requirements

Description

The CS4205 is an AC ’97 2.1 compliant stereo audio co-

dec designed for PC multimedia systems. It uses

industry leading CrystalClear



delta-sigma and mixed

signal technology. The CS405 is the first Cirrus AC ’97

audio codec to feature digital centric mixing and digital

effects. This advanced technology and these features

are designed to help enable the design of PC 99 and

PC 2001 compliant high-quality audio systems for desk-

top, portable, and entertainment PCs.

Coupling the CS4205 with a PCI audio accelerator or

core logic supporting the AC ’97 interface, implements a

cost effective, superior quality audio solution. The

CS4205 surpasses PC 99, PC 2001, and AC ’97 2.1 au-

dio quality standards.

ORDERING INFO

CS4205-KQ 48-pin TQFP

9x9x1.4 mm

AC-LINK AND AC ’97

REGISTERS

ANALOG INPUT MUX

AND OUTPUT MIXER

18 bit

ADC

(2ch)

INPUT

MUX

SYNC

BIT_CLK

SDATA_OUT

SDATA_IN

RESET#

ID0#

ID1#

TEST

PWR

MGT

SRC

PCM_DATA

AC-

LINK

’97

REG

SRC

MIC_PCM_DATA

18 bit

ADC

(1ch)

LINE

AUX

VIDEO

MIC1

MIC2

PHONE

PC_BEEP

SIGNAL

PROCESSING

ENGINE

GAIN / MUTE CONTROLS

MIXER / MUX SELECTS

INPUT

MIXER

OUTPUT

MIXER

20 bit

DAC

(2ch)

GPIO0/LRCLK

GPIO1/SDOUT

EAPD/SCLK

SPDO/SDO2

GPIO[2:4]/SDI[1:3]

ZSCLK,ZSDATA,ZLRCLK

GPIO

S/PDIF

SERIAL DATA PORT

SRC

ZV PORT

PCM_DATA

LINE_OUT

MONO_OUT

Preliminary Product Information

P.O. Box 17847, Austin, Texas 78760

(512) 445 7222 FAX: (512) 445 7581

http://www.cirrus.com

This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.



Cirrus Logic, Inc. 2001

APR ‘01

DS489PP2

CS4205

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ..................................................................7

Analog Characteristics ........................................................................................................7

Absolute Maximum Ratings ................................................................................................8

Recommended Operating Conditions.................................................................................8

AC ’97 Serial Port Timing..................................................................................................10

2. GENERAL DESCRIPTION ...............................................................................................13

2.1 AC-Link ......................................................................................................................13

2.2 Control Registers .......................................................................................................14

2.3 Sample Rate Converters ...........................................................................................14

2.4 Mixers ........................................................................................................................14

2.5 Input Mux ...................................................................................................................14

2.6 Volume Control ..........................................................................................................14

2.7 Dedicated Mic Record Path .......................................................................................14

3. DIGITAL SIGNAL PATHS ................................................................................................16

3.1 Analog Centric Mode .................................................................................................16

3.2 Digital Centric Mode ..................................................................................................17

3.3 Host Processing Mode ..............................................................................................17

3.4 Multi-Channel Mode ..................................................................................................17

4. AC-LINK FRAME DEFINITION ........................................................................................19

4.1 AC-Link Serial Data Output Frame ............................................................................20

4.1.1 Serial Data Output Slot Tags (Slot 0) ...........................................................20

4.1.2 Command Address Port (Slot 1) ..................................................................20

4.1.3 Command Data Port (Slot 2) ........................................................................21

4.1.4 PCM Playback Data (Slots 3-11) .................................................................21

4.1.5 GPIO Pin Control (Slot12) ............................................................................21

4.2 AC-Link Serial Data Input Frame ..............................................................................22

4.2.1 Serial Data Input Slot Tag Bits (Slot 0) ......................................................22

4.2.2 Status Address Port (Slot 1) .........................................................................22

4.2.3 Status Data Port (Slot 2) ..............................................................................23

4.2.4 PCM Capture Data (Slot 3-8) .......................................................................23

4.2.5 GPIO Pin Status (Slot 12) ...........................................................................23

4.3 AC-Link Protocol Violation - Loss of SYNC ...............................................................24

5. REGISTER INTERFACE

.............................................................................................25

5.1 Reset Register (Index 00h) ......................................................................................27

5.2 Master Volume Register (Index 02h) .......................................................................27

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/sales.cfm

Microsoft is a registered trademark of Microsoft Corporation in the United States and/or other countries.

Intel is a registered trademark of Intel Corporation.

CrystalClear is a registered trademark of Cirrus Logic.

Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-

mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information

contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any

kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third

parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publi-

cation may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise)

without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the

printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photo-

graphic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or

sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in

this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-

marks and service marks can be found at http://www.cirrus.com.

DS489PP2

CS4205

5.3 Mono Volume Register (Index 06h) .......................................................................... 28

5.4 Master Tone Control Register (Index 08h) ...............................................................28

5.5 PC_BEEP Volume Register (Index 0Ah) .................................................................. 29

5.6 Phone Volume Register (Index 0Ch) ........................................................................ 29

5.7 Microphone Volume Register (Index 0Eh) ................................................................ 30

5.8 Analog Mixer Input Gain Registers (Index 10h - 18h) .............................................. 31

5.9 Input Mux Select Register (Index 1Ah) .....................................................................32

5.10 Record Gain Register (Index 1Ch) ......................................................................... 33

5.11 Record Gain Mic Register (Index 1Eh) ................................................................... 33

5.12 General Purpose Register (Index 20h) ................................................................. 34

5.13 3D Control Register (Index 22h) ............................................................................. 34

5.14 Powerdown Control/Status Register (Index 26h) ................................................... 35

5.15 Extended Audio ID Register (Index 28h) ................................................................ 36

5.16 Extended Audio Status/Control Register (Index 2Ah) ............................................ 36

5.17 Audio Sample Rate Control Registers (Index 2Ch - 34h) ....................................... 37

5.18 Extended Modem ID Register (Index 3Ch) ............................................................ 38

5.19 Extended Modem Status/Control Register (Index 3Eh) ......................................... 38

5.20 GPIO Pin Configuration Register (Index 4Ch) ........................................................38

5.21 GPIO Pin Polarity/Type Configuration Register (Index 4Eh) .................................. 39

5.22 GPIO Pin Sticky Register (Index 50h) .................................................................... 39

5.23 GPIO Pin Wakeup Mask Register (Index 52h) ...................................................... 40

5.24 GPIO Pin Status Register (Index 54h) ................................................................... 40

5.25 AC Mode Control Register (Index 5Eh) .................................................................. 41

5.26 Misc. Crystal Control Register (Index 60h) ............................................................. 43

5.27 S/PDIF Control Register (Index 68h) ...................................................................... 44

5.28 Serial Port Control Register (Index 6Ah) ................................................................ 45

5.29 Special Feature Address Register (Index 6Ch) ...................................................... 46

5.30 Special Feature Data Register (Index 6Eh) ........................................................... 46

5.31 Digital Mixer Input Volume Registers (Index 6Eh, Address 00h - 05h) ..................46

5.32 Serial Data Port Volume Control Registers (Index 6Eh, Address 06h - 07h) ......... 47

5.33 Signal Processing Engine Control Register (Index 6Eh, Address 08h) ..................48

5.34 Internal Error Condition Control/Status Registers (Index 6Eh, Address 09h - 0Bh) 49

5.35 BIOS-Driver Interface Control Registers (Index 6Eh, Address 0Ch - 0Dh) ............ 50

5.36 ZV Port Control/Status Registers (Index 6Eh, Address 0Eh - 0Fh) ........................50

5.37 BIOS-Driver Interface Status Register (Index 7Ah) ................................................ 51

5.38 Vendor ID1 Register (Index 7Ch) ........................................................................... 52

5.39 Vendor ID2 Register (Index 7Eh) ........................................................................... 52

6. SERIAL DATA PORTS ..................................................................................................... 53

6.1 Overview ................................................................................................................... 53

6.2 Multi-Channel Expansion .......................................................................................... 53

6.3 Digital Docking .......................................................................................................... 54

6.4 Serial Data Formats .................................................................................................. 54

7. ZV PORT ........................................................................................................................... 56

8. SONY/PHILIPS DIGITAL INTERFACE (S/PDIF) ............................................................. 57

9. EXCLUSIVE FUNCTIONS ................................................................................................ 58

10. POWER MANAGEMENT ...............................................................................................59

10.1AC ’97 Reset Modes ................................................................................................. 59

10.1.1 Cold Reset ................................................................................................. 59

10.1.2 Warm Reset ...............................................................................................59

10.1.3 New Warm Reset ....................................................................................... 59

10.1.4 Register Reset ........................................................................................... 59

10.2Powerdown Controls ................................................................................................ 60

DS489PP2

CS4205

11. CLOCKING .....................................................................................................................62

11.1PLL Operation (External Clock) ................................................................................62

11.224.576 MHz Crystal Operation ..................................................................................62

11.3Secondary Codec Operation .....................................................................................62

12. ANALOG HARDWARE DESCRIPTION .........................................................................64

12.1Analog Inputs ............................................................................................................64

12.1.1 Line Inputs ..................................................................................................64

12.1.2 CD Input .....................................................................................................64

12.1.3 Microphone Inputs ......................................................................................65

12.1.4 PC Beep Input ............................................................................................65

12.1.5 Phone Input ................................................................................................65

12.2Analog Outputs .........................................................................................................65

12.2.1 Stereo Output .............................................................................................66

12.2.2 Mono Output ..............................................................................................66

12.3Miscellaneous Analog Signals ..................................................................................66

12.4Power Supplies .........................................................................................................66

12.5Reference Design .....................................................................................................66

13. GROUNDING AND LAYOUT ........................................................................................67

14. PIN DESCRIPTIONS ..................................................................................................69

Audio I/O Pins .................................................................................................................70

Analog Reference, Filter, and Configuration Pins ...........................................................71

AC-Link Pins ...................................................................................................................72

Clock and Configuration Pins ..........................................................................................72

Misc. Digital Interface Pins ..............................................................................................73

Power Supply Pins ..........................................................................................................74

15. PARAMETER AND TERM DEFINITIONS ......................................................................75

16. REFERENCE DESIGN ..................................................................................................77

17. REFERENCES ................................................................................................................78

18. PACKAGE DIMENSIONS ...............................................................................................79

DS489PP2

CS4205

LIST OF FIGURES

Figure 1. Power Up Timing ...............................................................................................11

Figure 2. Codec Ready from Start-up or Fault Condition ................................................. 11

Figure 3. Clocks................................................................................................................ 11

Figure 4. Data Setup and Hold .........................................................................................12

Figure 5. PR4 Powerdown and Warm Reset.................................................................... 12

Figure 6. Test Mode ......................................................................................................... 12

Figure 7. AC-link Connections .......................................................................................... 13

Figure 8. CS4205 Mixer Diagram ..................................................................................... 15

Figure 9. Digital Signal Path Overview ............................................................................. 16

Figure 10. Analog Centric Mode ....................................................................................... 18

Figure 11. Digital Centric Mode ........................................................................................ 18

Figure 12. Host Processing Mode .................................................................................... 18

Figure 13. Multi-Channel Mode ........................................................................................ 18

Figure 14. AC-link Input and Output Framing ................................................................... 19

Figure 15. Serial Data Port: Six Channel Circuit .............................................................. 53

Figure 16. Digital Docking Connection Diagram...............................................................54

Figure 17. Serial Data Format 0 (I2S) .............................................................................. 55

Figure 18. Serial Data Format 1 (Left Justified)................................................................ 55

Figure 19. Serial Data Format 2 (Right Justified, 20-bit data) .......................................... 55

Figure 20. Serial Data Format 3 (Right Justified, 16-bit data) .......................................... 55

Figure 21. ZV Port Format (I2S, 16-bit data) .................................................................... 56

Figure 22. S/PDIF Output ................................................................................................. 57

Figure 23. PLL External Loop Filter ..................................................................................62

Figure 24. External Crystal ...............................................................................................62

Figure 25. Line Input (Replicate for Video and AUX) ....................................................... 64

Figure 26. Differential 2 VRMS CD Input.......................................................................... 64

Figure 27. Differential 1 VRMS CD Input.......................................................................... 64

Figure 28. Microphone Input............................................................................................. 65

Figure 29. PC_BEEP Input ...............................................................................................65

Figure 30. Modem Connection .........................................................................................65

Figure 31. Stereo Output .................................................................................................. 66

Figure 32. +5V Analog Voltage Regulator ........................................................................ 66

Figure 33. Conceptual Layout for the CS4205 when in XTAL or OSC Clocking Modes .. 68

Figure 34. Pin Locations for the CS4205.......................................................................... 69

Figure 35. CS4205 Reference Design.............................................................................. 77

DS489PP2

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