Philips Semiconductors
Product specification
N-channel enhancement mode
TrenchMOS
TM
transistor
GENERAL DESCRIPTION
N-channel enhancement mode
standard level field-effect power
transistor in a plastic envelope using
’trench’ technology. The device
features very low on-state resistance
and has integral zener diodes giving
ESD protection up to 2kV. It is
intended for use in switched mode
power supplies and general purpose
switching applications.
IRFZ44N
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
tot
T
j
R
DS(ON)
PARAMETER
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
V
GS
= 10 V
MAX.
55
49
110
175
22
UNIT
V
A
W
˚C
mΩ
PINNING - TO220AB
PIN
1
2
3
tab
gate
drain
source
drain
DESCRIPTION
PIN CONFIGURATION
tab
SYMBOL
d
g
s
1 23
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
V
DS
V
DGR
±V
GS
I
D
I
D
I
DM
P
tot
T
stg
, T
j
PARAMETER
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
CONDITIONS
-
R
GS
= 20 kΩ
-
T
mb
= 25 ˚C
T
mb
= 100 ˚C
T
mb
= 25 ˚C
T
mb
= 25 ˚C
-
MIN.
-
-
-
-
-
-
-
- 55
MAX.
55
55
20
49
35
160
110
175
UNIT
V
V
V
A
A
A
W
˚C
ESD LIMITING VALUE
SYMBOL
V
C
PARAMETER
Electrostatic discharge capacitor
voltage, all pins
CONDITIONS
Human body model
(100 pF, 1.5 kΩ)
MIN.
-
MAX.
2
UNIT
kV
THERMAL RESISTANCES
SYMBOL
R
th j-mb
R
th j-a
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
-
in free air
TYP.
-
60
MAX.
1.4
-
UNIT
K/W
K/W
February 1999
1
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
TrenchMOS
TM
transistor
STATIC CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL
V
(BR)DSS
V
GS(TO)
I
DSS
I
GSS
±V
(BR)GSS
R
DS(ON)
PARAMETER
Drain-source breakdown
voltage
Gate threshold voltage
Zero gate voltage drain current
Gate source leakage current
CONDITIONS
V
GS
= 0 V; I
D
= 0.25 mA;
T
j
= -55˚C
V
DS
= V
GS
; I
D
= 1 mA
T
j
= 175˚C
T
j
= -55˚C
V
DS
= 55 V; V
GS
= 0 V;
V
GS
=
±10
V; V
DS
= 0 V
T
j
= 175˚C
T
j
= 175˚C
T
j
= 175˚C
MIN.
55
50
2.0
1.0
-
-
-
-
-
16
-
-
TYP.
-
-
3.0
-
-
0.05
-
0.04
-
-
15
-
IRFZ44N
MAX.
-
-
4.0
-
4.4
10
500
1
20
-
22
42
UNIT
V
V
V
V
µA
µA
µA
µA
V
mΩ
mΩ
Gate source breakdown voltage I
G
=
±1
mA;
Drain-source on-state
V
GS
= 10 V; I
D
= 25 A
resistance
DYNAMIC CHARACTERISTICS
T
mb
= 25˚C unless otherwise specified
SYMBOL
g
fs
C
iss
C
oss
C
rss
Q
g
Q
gs
Q
gd
t
d on
t
r
t
d off
t
f
L
d
L
d
L
s
PARAMETER
Forward transconductance
Input capacitance
Output capacitance
Feedback capacitance
Total gate charge
Gate-cource charge
Gate-drain (miller) charge
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
Internal drain inductance
Internal drain inductance
Internal source inductance
CONDITIONS
V
DS
= 25 V; I
D
= 25 A
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
MIN.
6
-
-
-
-
-
-
-
-
-
-
-
-
-
TYP.
-
1350
330
155
-
-
-
18
50
40
30
3.5
4.5
7.5
MAX.
-
1800
400
215
62
15
26
26
75
50
40
-
-
-
UNIT
S
pF
pF
pF
nC
nC
nC
ns
ns
ns
ns
nH
nH
nH
V
DD
= 44 V; I
D
= 50 A; V
GS
= 10 V
V
DD
= 30 V; I
D
= 25 A;
V
GS
= 10 V; R
G
= 10
Ω
Resistive load
Measured from contact screw on
tab to centre of die
Measured from drain lead 6 mm
from package to centre of die
Measured from source lead 6 mm
from package to source bond pad
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL
I
DR
I
DRM
V
SD
t
rr
Q
rr
PARAMETER
Continuous reverse drain
current
Pulsed reverse drain current
Diode forward voltage
Reverse recovery time
Reverse recovery charge
CONDITIONS
MIN.
-
I
F
= 25 A; V
GS
= 0 V
I
F
= 40 A; V
GS
= 0 V
I
F
= 40 A; -dI
F
/dt = 100 A/µs;
V
GS
= -10 V; V
R
= 30 V
-
-
-
-
-
TYP.
-
-
0.95
1.0
47
0.15
MAX.
49
160
1.2
-
-
-
UNIT
A
A
V
ns
µC
February 1999
2
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
TrenchMOS
TM
transistor
AVALANCHE LIMITING VALUE
SYMBOL
W
DSS
PARAMETER
Drain-source non-repetitive
unclamped inductive turn-off
energy
CONDITIONS
I
D
= 45 A; V
DD
≤
25 V;
V
GS
= 10 V; R
GS
= 50
Ω;
T
mb
= 25 ˚C
MIN.
-
TYP.
-
IRFZ44N
MAX.
110
UNIT
mJ
120
110
100
90
80
70
60
50
40
30
20
10
0
PD%
Normalised Power Derating
1000
ID/A
RDS(ON) =VDS/ID
100
tp =
1 us
10us
100 us
DC
10
1 ms
10ms
100ms
0
20
40
60
80 100
Tmb / C
120
140
160
180
1
1
10
VDS/V
100
Fig.1. Normalised power dissipation.
PD% = 100
⋅
P
D
/P
D 25 ˚C
= f(T
mb
)
Normalised Current Derating
Fig.3. Safe operating area. T
mb
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Zth/(K/W)
120
110
100
90
80
70
60
50
40
30
20
10
0
ID%
10
1
0.5
0.2
0.1
0.1
0.05
0.02
0.01
0
t
p
T
t
P
D
t
p
D=
T
0
20
40
60
80 100
Tmb / C
120
140
160
180
0.001
1E-06
0.0001
0.01
t/s
1
100
Fig.2. Normalised continuous drain current.
ID% = 100
⋅
I
D
/I
D 25 ˚C
= f(T
mb
); conditions: V
GS
≥
10 V
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
February 1999
3
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
TrenchMOS
TM
transistor
IRFZ44N
100
16
10
9
8.5
30
VGS/V =
8.0
7.5
ID/A
80
gfs/S
25
20
60
7.0
15
6.5
40
6.0
20
10
5.5
5.0
4.5
10
4.0
5
0
0
0
2
4
VDS/V
6
8
0
20
40
ID/A
60
80
100
Fig.5. Typical output characteristics, T
j
= 25 ˚C.
I
D
= f(V
DS
); parameter V
GS
RDS(ON)/mOhm
VGS/V =
6
Fig.8. Typical transconductance, T
j
= 25 ˚C.
g
fs
= f(I
D
); conditions: V
DS
= 25 V
BUK959-60
40
2.5
a
Rds(on) normlised to 25degC
35
2
30
6.5
7
25
8
20
9
10
1.5
1
15
10
0
10
20
30
40
ID/A
50
60
70
80
90
0.5
-100
-50
0
50
Tmb / degC
100
150
200
Fig.6. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(I
D
); parameter V
GS
100
ID/A
80
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
); I
D
= 25 A; V
GS
= 10 V
VGS(TO) / V
max.
4
typ.
BUK759-60
5
60
3
min.
40
2
20
Tj/C =
0
175
25
1
0
2
4
6
VGS/V
8
10
12
0
-100
-50
0
50
Tj / C
100
150
200
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
) ; conditions: V
DS
= 25 V; parameter T
j
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
February 1999
4
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
TrenchMOS
TM
transistor
IRFZ44N
1E-01
Sub-Threshold Conduction
100
IF/A
80
1E-02
2%
typ
98%
60
Tj/C =
40
175
25
1E-03
1E-04
20
1E-05
0
1E-06
0
0.2
0.4
0
1
2
3
4
5
0.6
0.8
VSDS/V
1
1.2
1.4
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C; V
DS
= V
GS
2.5
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
WDSS%
120
110
100
90
80
2
Thousands pF
1.5
Ciss
1
70
60
50
40
30
20
Coss
Crss
.5
10
0
20
40
60
80
100
120
Tmb / C
140
160
180
0
0.01
0.1
1
VDS/V
10
100
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
12
VGS/V
10
VDS = 14V
8
VDS = 44V
6
Fig.15. Normalised avalanche energy rating.
W
DSS
% = f(T
mb
); conditions: I
D
= 49 A
+
L
VDS
VGS
0
RGS
T.U.T.
R 01
shunt
VDD
-
-ID/100
4
2
0
0
10
20
QG/nC
30
40
50
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); conditions: I
D
= 50 A; parameter V
DS
Fig.16. Avalanche energy test circuit.
2
W
DSS
=
0.5
⋅
LI
D
⋅
BV
DSS
/(BV
DSS
−
V
DD
)
February 1999
5
Rev 1.000
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