CS4338 datasheet, PDF - EEWORLD Datasheet

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CS4338: Description8-pin, 24-bit, 96 khz stereo D/A converter; Categorysemiconductor Discrete semiconductor; File Size684KB，26 Pages; ManufacturerCirrus Logic; Websitehttp://www.cirrus.com; Environmental Compliance

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CS4338 Overview

8-pin, 24-bit, 96 khz stereo D/A converter

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CS4334/5/6/7/8/9

8-Pin, 24-Bit, 96 kHz Stereo D/A Converter

Features

Complete Stereo DAC System: Interpolation,

Description

The CS4334 family members are complete, stereo digi-

tal-to-analog output systems including interpolation, 1-bit

D/A conversion and output analog filtering in an 8-pin

package. The CS4334/5/6/7/8/9 support all major audio

data interface formats, and the individual devices differ

only in the supported interface format.

The CS4334 family is based on delta-sigma modulation,

where the modulator output controls the reference volt-

age input to an ultra-linear analog low-pass filter. This

architecture allows for infinite adjustment of sample rate

between 2 kHz and 100 kHz simply by changing the

master clock frequency.

The CS4334 family contains on-chip digital de-empha-

sis, operates from a single +5V power supply, and

requires minimal support circuitry. These features are

ideal for set-top boxes, DVD players, SVCD players, and

A/V receivers.

ORDERING INFORMATION

See page 23

D/A, Output Analog Filtering

24-Bit Conversion

96 dB Dynamic Range

-88 dB THD+N

Low Clock Jitter Sensitivity

Single +5 V Power Supply

Filtered Line Level Outputs

On-Chip Digital De-emphasis

Popgaurd

Technology

Functionally Compatible with CS4330/31/33

DEM/SCLK

LRCK

SDATA

Serial Input

Interface

De-emphasis

AGND

Voltage Reference

Interpolator

∆Σ

Modulator

DAC

Analog

Low-Pass

Filter

AOUTL

Interpolator

∆Σ

Modulator

MCLK

DAC

Analog

Low-Pass

Filter

AOUTR

Preliminary Product Information

P.O. Box 17847, Austin, Texas 78760

(512) 445 7222 FAX: (512) 445 7581

http://www.cirrus.com

This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

Cirrus Logic, Inc. 1999

SEP ‘99

DS248PP3

CS4334/5/6/7/8/9

TABLE OF CONTENTS

1. CHARACTERISTICS/SPECIFICATIONS ...................................................... 4

ANALOG CHARACTERISTICS................................................................... 4

POWER AND THERMAL CHARACTERISTICS ......................................... 6

DIGITAL CHARACTERISTICS.................................................................... 7

ABSOLUTE MAXIMUM RATINGS .............................................................. 7

RECOMMENDED OPERATING CONDITIONS .......................................... 7

SWITCHING CHARACTERISTICS ............................................................. 8

2. TYPICAL CONNECTION DIAGRAM ........................................................... 10

3. GENERAL DESCRIPTION .......................................................................... 11

3.1 Digital Interpolation Filter ................................................................... 11

3.2 Delta-Sigma Modulator ...................................................................... 11

3.3 Switched-Capacitor DAC ................................................................... 11

3.4 Analog Low-Pass Filter ...................................................................... 11

4. SYSTEM DESIGN ........................................................................................ 12

4.1 Master Clock ...................................................................................... 12

4.2 Serial Clock ........................................................................................ 12

4.2.1 External Serial Clock Mode ...................................................... 12

4.2.2 Internal Serial Clock Mode ....................................................... 12

4.3 De-Emphasis ..................................................................................... 12

4.4 Initialization and Power-Down ........................................................... 12

4.5 Output Transient Control ................................................................... 13

4.6 Grounding and Power Supply Decoupling ......................................... 13

4.7 Analog Output and Filtering ............................................................... 13

4.8 Overall Base-Rate Frequency Response .......................................... 17

4.9 Overall High-Rate Frequency Response ........................................... 18

4.10 Base Rate Mode Performance Plots ............................................... 19

4.11 High Rate Mode Performance Plots ................................................ 20

5. PIN DESCRIPTIONS ................................................................................... 21

6. PARAMETER DEFINITIONS ....................................................................... 22

7. REFERENCES ............................................................................................. 22

8. ORDERING INFORMATION: ...................................................................... 23

9. FUNCTIONAL COMPATIBILITY ................................................................. 23

10. PACKAGE DIMENSIONS .......................................................................... 24

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/

Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-

mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information

contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of

any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights

of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of

this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or

otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no

part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,

photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture

or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing

in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-

marks and service marks can be found at http://www.cirrus.com.

DS248PP3

CS4334/5/6/7/8/9

LIST OF FIGURES

Figure 1.Output Test Load .................................................................................... 6

Figure 2.Maximum Loading................................................................................... 6

Figure 3.Power vs. Sample Rate .......................................................................... 6

Figure 4.External Serial Mode Input Timing.......................................................... 9

Figure 5.Internal Serial Mode Input Timing ........................................................... 9

Figure 6. Internal Serial Clock Generation ............................................................ 9

Figure 7.Recommended Connection Diagram.................................................... 10

Figure 8.System Block Diagram.......................................................................... 11

Figure 9.De-Emphasis Curve (Fs = 44.1kHz) ..................................................... 13

Figure 10.CS4334 Data Format (I

S).................................................................. 14

Figure 11.CS4335 Data Format .......................................................................... 14

Figure 12.CS4336 Data Format .......................................................................... 14

Figure 13.CS4337 Data Format .......................................................................... 15

Figure 14.CS4338 Data Format .......................................................................... 15

Figure 15.CS4339 Data Format .......................................................................... 15

Figure 16.CS4334/5/6/7/8/9 Initialization and Power-Down Sequence .............. 16

Figure 17.Stopband Rejection............................................................................. 17

Figure 18.Transition Band................................................................................... 17

Figure 19.Transition Band................................................................................... 17

Figure 20.Passband Ripple................................................................................. 17

Figure 21.Stopband Rejection............................................................................. 18

Figure 22.Transition Band................................................................................... 18

Figure 23.Transition Band................................................................................... 18

Figure 24.Passband Ripple................................................................................. 18

Figure 25.0 dBFS FFT (BRM) ............................................................................. 19

Figure 26. -60 dBFS FFT (BRM)......................................................................... 19

Figure 27.Idle Channel Noise FFT (BRM)........................................................... 19

Figure 28.Twin Tone IMD FFT (BRM)................................................................. 19

Figure 29.THD+N vs. Amplitude (BRM) .............................................................. 19

Figure 30.THD+N vs. Frequency (BRM) ............................................................. 19

Figure 31.0 dBFS FFT (HRM)............................................................................. 20

Figure 32. -60 dBFS FFT (HRM)......................................................................... 20

Figure 33.Idle Channel Noise FFT (HRM) .......................................................... 20

Figure 34.Twin Tone IMD FFT (HRM) ................................................................ 20

Figure 35.THD+N vs. Amplitude (HRM).............................................................. 20

Figure 36. THD+N vs. Frequency (HRM)............................................................ 20

DS248PP3

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