PCF85116-3
2048
×
8-bit CMOS EEPROM with I
2
C-bus interface
Rev. 04 — 25 October 2004
Product data
1. Description
The PCF85116-3 is an 16 kbits (2048
×
8-bit) floating gate Electrically Erasable
Programmable Read Only Memory (EEPROM). By using redundant EEPROM cells it
is fault tolerant to single bit errors. In most cases multi bit errors are also covered.
This feature dramatically increases reliability compared to conventional EEPROM
memories. Power consumption is low due to the full CMOS technology used. The
programming voltage is generated on-chip, using a voltage multiplier.
As data bytes are received and transmitted via the serial I
2
C-bus, a package using
eight pins is sufficient. Only one PCF85116-3 device is required to support all eight
blocks of 256
×
8-bit each.
Timing of the E/W cycle is carried out internally, thus no external components are
required. A write-protection input at pin 7 (WP) allows disabling of write-commands
from the master by a hardware signal. When pin 7 is HIGH, data in the EEPROM are
protected. The data bytes received will not be acknowledged by the PCF85116-3 and
the EEPROM contents are not changed.
Remark:
The PCF85116-3 is pin and address compatible to the PCx85xxC-2 family.
The PCF85116-3 covers the whole address space of 16 kbits; address inputs are no
longer needed. Therefore, pins 1 to 3 are not connected. The write-protection input
(WP) is on pin 7.
2. Features
s
Low power CMOS:
x
maximum operating current 1.0 mA
x
maximum standby current 10
µA
(at 5.5 V), typical 4
µA
s
Non-volatile storage of 16 kbits organized as eight blocks of 256
×
8-bit each
s
Single supply with full operation down to 2.7 V
s
On-chip voltage multiplier
s
Serial input/output I
2
C-bus (100 kbit/s standard-mode and 400 kbit/s fast-mode)
s
Write operations: multi byte write mode up to 32 bytes
s
Write-protection input
s
Read operations:
x
sequential read
x
random read
s
Internal timer for writing (no external components)
s
Power-on reset
s
High reliability by using redundant EEPROM cells
Philips Semiconductors
PCF85116-3
2048
×
8-bit CMOS EEPROM with I
2
C-bus interface
Endurance: 1000000 Erase/Write (E/W) cycles at T
amb
= 22
°C
20 years non-volatile data retention time (minimum)
Pin and address compatible to the PCx85xxC-2 family
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101
s
Latch-up testing is done to JESDEC Standard JESD78 which exceeds 100 mA
s
Offered in DIP and SO packages
s
s
s
s
3. Quick reference data
Table 1:
Symbol
V
DD
I
DDR
I
DDW
I
stb
Quick reference data
Parameter
supply voltage
supply current read
supply current E/W
standby supply current
f
SCL
= 400 kHz; V
DD
= 5.5 V
f
SCL
= 400 kHz; V
DD
= 5.5 V
V
DD
= 2.7 V
V
DD
= 5.5 V
Conditions
Min
2.7
-
-
-
-
Typ
-
-
-
-
-
Max
5.5
1.0
1.0
6
10
Unit
V
mA
mA
µA
µA
4. Ordering information
Table 2:
Ordering information
Package
Name
PCF85116-3P/01
PCF85116-3T/01
DIP8
SO8
Description
plastic dual in-line package; 8 leads (300 mil)
plastic small outline package; 8 leads;
body width 3.9 mm
Version
SOT97-1
SOT96-1
Type number
4.1 Ordering options
Table 3:
Ordering options
Topside mark
PCF85116-3
85116-3
Type number
PCF85116-3P/01
PCF85116-3T/01
9397 750 14217
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 — 25 October 2004
2 of 21
Philips Semiconductors
PCF85116-3
2048
×
8-bit CMOS EEPROM with I
2
C-bus interface
5. Block diagram
WP
PCF85116-3
SCL
SDA
6
5
INPUT
FILTER
I
2
C-BUS CONTROL LOGIC
7
n
TEST MODE
REGISTER
ADDRESS
COMPARATOR
SHIFT
REGISTER
ADDRESS
POINTER
SEQUENCER
5
COLUMN DECODER
HV
GENERATOR
PAGE REGISTER
6
VDD
8
POWER-ON-RESET
EEPROM ARRAY
(8
×
256
×
8)
ROW
DEC
DIVIDER
OSCILLATOR
4
002aaa338
VSS
Fig 1. Block diagram.
9397 750 14217
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 — 25 October 2004
3 of 21
Philips Semiconductors
PCF85116-3
2048
×
8-bit CMOS EEPROM with I
2
C-bus interface
6. Pinning information
6.1 Pinning
n.c.
1
8 V DD
7
WP
SCL
SDA
n.c. 2
PCF85116-3
n.c. 3
VSS 4
002aaa284
6
5
Fig 2. Pin configuration.
6.2 Pin description
Table 4:
Symbol
n.c.
n.c.
n.c.
V
SS
SDA
SCL
WP
V
DD
Pin description
Pin
1
2
3
4
5
6
7
8
Description
not connected
not connected
not connected
negative supply voltage
serial data input/output (I
2
C-bus)
serial clock input (I
2
C-bus)
active HIGH write-protection input
positive supply voltage
7. Device selection
Table 5:
Selection
Bit
Device
[1]
Device selection code
Device code
B7
[1]
1
B6
0
B5
1
B4
0
B3
Chip enable
B2
B1
MEM SEL 2 MEM SEL 1 MEM SEL 0
R/W
B0
R/W
The Most Significant Bit (MSB) ‘B7’ is sent first.
9397 750 14217
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 — 25 October 2004
4 of 21
Philips Semiconductors
PCF85116-3
2048
×
8-bit CMOS EEPROM with I
2
C-bus interface
8. Functional description
8.1 I
2
C-bus protocol
The I
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The
serial bus consists of two bidirectional lines; one for data signals (SDA), and one for
clock signals (SCL).
Both the SDA and SCL lines must be connected to a positive supply voltage via a
pull-up resistor.
The following protocol has been defined:
•
Data transfer may be initiated only when the bus is not busy.
•
During data transfer, the data line must remain stable whenever the clock line is
HIGH. Changes in the data line while the clock line is HIGH will be interpreted as
control signals.
8.1.1
Bus conditions
The following bus conditions have been defined:
Bus not busy —
Both data and clock lines remain HIGH.
Start data transfer —
A change in the state of the data line, from HIGH-to-LOW,
while the clock is HIGH, defines the START condition.
Stop data transfer —
A change in the state of the data line, from LOW-to-HIGH,
while the clock is HIGH, defines the STOP condition.
Data valid —
The state of the data line represents valid data when, after a START
condition, the data line is stable for the duration of the HIGH period of the clock
signal. There is one clock pulse per bit of data.
8.1.2
Data transfer
Each data transfer is initiated with a START condition and terminated with a STOP
condition. The number of the data bytes transferred between the START and STOP
conditions is limited to 32 bytes in the E/W mode.
Data transfer is unlimited in the read mode. The information is transmitted in bytes
and each receiver acknowledges with a ninth bit.
Within the I
2
C-bus specifications a standard-speed mode (100 kHz clock rate), a
fast-speed mode (400 kHz clock rate) and a high-speed mode (3.2 MHz clock rate)
are defined. The PCF85116-3 operates in only the standard and fast-speed modes.
By definition, a device that sends a signal is called a ‘transmitter’, and the device
which receives the signal is called a ‘receiver’. The device which controls the signal is
called the ‘master’. The devices that are controlled by the master are called ‘slaves’.
Each byte is followed by one acknowledge bit. This acknowledge bit is a HIGH level,
put on the bus by the transmitter. The master generates an extra acknowledge related
clock pulse. The slave receiver which is addressed is obliged to generate an
acknowledge after the reception of each byte.
9397 750 14217
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 — 25 October 2004
5 of 21
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