GAL20V8
High Performance E
2
CMOS PLD
Generic Array Logic™
Features
• HIGH PERFORMANCE E
2
CMOS
®
TECHNOLOGY
— 5 ns Maximum Propagation Delay
— Fmax = 166 MHz
— 4 ns Maximum from Clock Input to Data Output
— UltraMOS
®
Advanced CMOS Technology
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
— 75mA Typ Icc on Low Power Device
— 45mA Typ Icc on Quarter Power Device
• ACTIVE PULL-UPS ON ALL PINS
• E
2
CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Also Emulates 24-pin PAL
®
Devices with Full Function/
Fuse Map/Parametric Compatibility
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
I
8
I/O/Q
OE
Functional Block Diagram
I/CLK
I
I
IMUX
CLK
8
OLMC
I
8
I
OLMC
I/O/Q
I/O/Q
PROGRAMMABLE
AND-ARRAY
(64 X 40)
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
I
OLMC
I
IMUX
I/OE
Description
The GAL20V8C, at 5ns maximum propagation delay time, com-
bines a high performance CMOS process with Electrically Eras-
able (E
2
) floating gate technology to provide the highest speed
performance available in the PLD market. High speed erase times
(<100ms) allow the devices to be reprogrammed quickly and ef-
ficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configura-
tions possible with the GAL20V8 are the PAL architectures listed
in the table of the macrocell description section. GAL20V8 devices
are capable of emulating any of these PAL architectures with full
function/fuse map/parametric compatibility.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Pin Configuration
DIP
PLCC
I/CLK
I/CLK
Vcc
NC
I/O/Q
1
24
Vcc
I
I/O/Q
I
I
I/O/Q
I/O/Q
I
I
I
4
I
I
I
NC
I
I
I
11
12
9
7
5
2
28
26
25
I
I
I
I
I
I
I
I
GND
12
6
GAL
20V8
18
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
13
I/OE
23
I/O/Q
NC
GAL20V8
Top View
14
16
21
I/O/Q
I/O/Q
19
18
I/O/Q
I
I
NC
GND
I/OE
I
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
I/O/Q
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
August 2000
20v8_04
1
Specifications
GAL20V8
GAL20V8 Ordering Information
Commercial Grade Specifications
Tpd (ns)
5
7.5
Tsu (ns)
3
7
Tco (ns)
4
5
Icc (mA)
115
115
11 5
11 5
Ordering #
GAL20V8C-5LJ
GAL20V8C-7LJ
GAL20V8B-7LP
GAL20V8B-7LJ
GAL20V8C-10LJ
GAL20V8B-10LP
GAL20V8B-10LJ
GAL20V8B-15QP
GAL20V8B-15QJ
GAL20V8B-15LP
GAL20V8B-15LJ
GAL20V8B-25QP
GAL20V8B-25QJ
GAL20V8B-25LP
GAL20V8B-25LJ
Package
28-Lead PLCC
28-Lead PLCC
24-Pin Plastic DIP
28-Lead PLCC
28-Lead PLCC
24-Pin Plastic DIP
28-Lead PLCC
24-Pin Plastic DIP
28-Lead PLCC
24-Pin Plastic DIP
28-Lead PLCC
24-Pin Plastic DIP
28-Lead PLCC
24-Pin Plastic DIP
28-Lead PLCC
10
10
7
115
115
115
15
12
10
55
55
90
90
25
15
12
55
55
90
90
Industrial Grade Specifications
Tpd (ns)
10
Tsu (ns)
10
Tco (ns)
7
Icc (mA)
130
130
130
Ordering #
GAL20V8C-10LJI
GAL20V8B-10LPI
GAL20V8B-10LJI
GAL20V8B-15LPI
GAL20V8B-15LJI
GAL20V8B-20QPI
GAL20V8B-20QJI
GAL20V8B-25QPI
GAL20V8B-25QJI
GAL20V8B-25LPI
GAL20V8B-25LJI
Package
28-Lead PLCC
24-Pin Plastic DIP
28-Lead PLCC
24-Pin Plastic DIP
28-Lead PLCC
24-Pin Plastic DIP
28-Lead PLCC
24-Pin Plastic DIP
28-Lead PLCC
24-Pin Plastic DIP
28-Lead PLCC
15
12
10
130
130
20
13
11
65
65
25
15
12
65
65
130
130
Part Number Description
XXXXXXXX _ XX
X X X
GAL20V8C
Device Name
GAL20V8B
Speed (ns)
L = Low Power
Power
Q = Quarter Power
Grade
Blank = Commercial
I = Industrial
Package
P = Plastic DIP
J = PLCC
2
Specifications
GAL20V8
Output Logic Macrocell (OLMC)
The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accom-
plished by development software/hardware and is completely trans-
parent to the user.
There are three global OLMC configuration modes possible:
simple, complex,
and
registered.
Details of each of these modes
is illustrated in the following pages. Two global bits, SYN and AC0,
control the mode configuration for all macrocells. The XOR bit of
each macrocell controls the polarity of the output in any of the three
modes, while the AC1 bit of each of the macrocells controls the in-
put/output configuration. These two global and 16 individual archi-
tecture bits define all possible configurations in a GAL20V8 . The
information given on these architecture bits is only to give a bet-
ter understanding of the device. Compiler software will transpar-
ently set these architecture bits from the pin definitions, so the user
should not need to directly manipulate these architecture bits.
The following is a list of the PAL architectures that the GAL20V8
can emulate. It also shows the OLMC mode under which the
devices emulate the PAL architecture.
PAL Architectures
Emulated by GAL20V8
20R8
20R6
20R4
20RP8
20RP6
20RP4
20L8
20H8
20P8
14L8
16L6
18L4
20L2
14H8
16H6
18H4
20H2
14P8
16P6
18P4
20P2
GAL20V8
Global OLMC Mode
Registered
Registered
Registered
Registered
Registered
Registered
Complex
Complex
Complex
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Compiler Support for OLMC
Software compilers support the three different global OLMC modes
as different device types. These device types are listed in the table
below. Most compilers have the ability to automatically select the
device type, generally based on the register usage and output
enable (OE) usage. Register usage on the device forces the soft-
ware to choose the registered mode. All combinatorial outputs with
OE controlled by the product term will force the software to choose
the complex mode. The software will choose the simple mode only
when all outputs are dedicated combinatorial without OE control.
The different device types listed in the table can be used to override
the automatic device selection by the software. For further details,
refer to the compiler software manuals.
When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each mode.
In
registered mode
pin 1 and pin 13 (DIP pinout) are permanently
configured as clock and output enable, respectively. These pins
cannot be configured as dedicated inputs in the registered mode.
In
complex mode
pin 1 and pin 13 become dedicated inputs and
use the feedback paths of pin 22 and pin 15 respectively. Because
of this feedback path usage, pin 22 and pin 15 do not have the
feedback option in this mode.
In
simple mode
all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
18 and 19) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.
Registered
ABEL
CUPL
LOG/iC
OrCAD-PLD
PLDesigner
TANGO-PLD
P20V8R
G20V8MS
GAL20V8_R
"Registered"
1
P20V8R
2
G20V8R
Complex
P20V8C
G20V8MA
GAL20V8_C7
"Complex"
1
P20V8C
2
G20V8C
Simple
P20V8AS
G20V8AS
GAL20V8_C8
"Simple"
1
P20V8C
2
G20V8AS
3
Auto Mode Select
P20V8
G20V8
GAL20V8
GAL20V8A
P20V8A
G20V8
1) Used with
Configuration
keyword.
2) Prior to Version 2.0 support.
3) Supported on Version 1.20 or later.
3
Specifications
GAL20V8
Registered Mode
In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.
Architecture configurations available in this mode are similar to the
common 20R8 and 20RP4 devices with various permutations of
polarity, I/O and register placement.
All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or I/
O. Up to eight registers or up to eight I/Os are possible in this mode.
Dedicated input or output functions can be implemented as sub-
sets of the I/O function.
Registered outputs have eight product terms per output. I/Os have
seven product terms per output.
The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product Term Disable (PTD) fuses, are shown
on the logic diagram on the following page.
CLK
Registered Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this output configuration.
- Pin 1 controls common CLK for the registered outputs.
- Pin 13 controls common
OE
for the registered outputs.
- Pin 1 & Pin 13 are permanently configured as CLK &
OE
for registered output configuration.
D
Q
Q
XOR
OE
Combinatorial Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this output configuration.
- Pin 1 & Pin 13 are permanently configured as CLK &
OE
for registered output configuration..
XOR
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
4
Specifications
GAL20V8
Registered Mode Logic Diagram
DIP (PLCC) Package Pinouts
1(2)
2640
0
4
8
12
16
20
24
28
32
36
PTD
2(3)
0000
23(27)
OLMC
XOR-2560
AC1-2632
22(26)
0280
3(4)
0320
OLMC
21(25)
XOR-2561
AC1-2633
0600
4(5)
0640
OLMC
20(24)
XOR-2562
AC1-2634
0920
5(6)
0960
OLMC
19(23)
XOR-2563
AC1-2635
1240
6(7)
1280
OLMC
XOR-2564
AC1-2636
18(21)
1560
7(9)
1600
OLMC
XOR-2565
AC1-2637
17(20)
1880
8(10)
1920
OLMC
XOR-2566
AC1-2638
16(19)
2200
9(11)
2240
OLMC
XOR-2567
AC1-2639
15(18)
2520
10(12)
11(13)
14(17)
OE
2703
13(16)
SYN-2704
AC0-2705
5
Embedded System
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