GAL20V8B-10LI datasheet, PDF - EEWORLD Datasheet

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GAL20V8B-10LI: Descriptionhigh performance e2cmos pld generic array logic; File Size304KB，23 Pages; ManufacturerAll Sensors

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GAL20V8B-10LI Overview

high performance e2cmos pld generic array logic

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GAL20V8

High Performance E

CMOS PLD

Generic Array Logic™

Features

• HIGH PERFORMANCE E

CMOS

TECHNOLOGY

— 5 ns Maximum Propagation Delay

— Fmax = 166 MHz

— 4 ns Maximum from Clock Input to Data Output

— UltraMOS

Advanced CMOS Technology

• 50% to 75% REDUCTION IN POWER FROM BIPOLAR

— 75mA Typ Icc on Low Power Device

— 45mA Typ Icc on Quarter Power Device

• ACTIVE PULL-UPS ON ALL PINS

• E

CELL TECHNOLOGY

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

• EIGHT OUTPUT LOGIC MACROCELLS

— Maximum Flexibility for Complex Logic Designs

— Programmable Output Polarity

— Also Emulates 24-pin PAL

Devices with Full Function/

Fuse Map/Parametric Compatibility

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS

— 100% Functional Testability

• APPLICATIONS INCLUDE:

— DMA Control

— State Machine Control

— High Speed Graphics Processing

— Standard Logic Speed Upgrade

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

I/O/Q

Functional Block Diagram

I/CLK

IMUX

CLK

OLMC

I/O/Q

PROGRAMMABLE

AND-ARRAY

(64 X 40)

OLMC

I/O/Q

OLMC

I/O/Q

OLMC

I/O/Q

OLMC

I/O/Q

OLMC

I/O/Q

OLMC

IMUX

I/OE

Description

The GAL20V8C, at 5ns maximum propagation delay time, com-

bines a high performance CMOS process with Electrically Eras-

able (E

) floating gate technology to provide the highest speed

performance available in the PLD market. High speed erase times

(<100ms) allow the devices to be reprogrammed quickly and ef-

ficiently.

The generic architecture provides maximum design flexibility by

allowing the Output Logic Macrocell (OLMC) to be configured by

the user. An important subset of the many architecture configura-

tions possible with the GAL20V8 are the PAL architectures listed

in the table of the macrocell description section. GAL20V8 devices

are capable of emulating any of these PAL architectures with full

function/fuse map/parametric compatibility.

Unique test circuitry and reprogrammable cells allow complete AC,

DC, and functional testing during manufacture. As a result, Lattice

Semiconductor delivers 100% field programmability and function-

ality of all GAL products. In addition, 100 erase/write cycles and

data retention in excess of 20 years are specified.

Pin Configuration

DIP

PLCC

I/CLK

Vcc

I/O/Q

Vcc

I/O/Q

GND

GAL

20V8

I/O/Q

I/OE

I/O/Q

GAL20V8

Top View

I/O/Q

GND

I/OE

to change without notice.

I/O/Q

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

August 2000

20v8_04

GAL20V8B-10LI Related Products

	GAL20V8B-10LI	GAL20V8B-7LI	GAL20V8C-10LP	GAL20V8C-5LJ	GAL20V8
Description	high performance e2cmos pld generic array logic	high performance e2cmos pld generic array logic	high performance e2cmos pld generic array logic	high performance e2cmos pld generic array logic	high performance e2cmos pld generic array logic

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