RENESAS LSIs
M5M5V208AKV
2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM
DESCRIPTION
The M5M5V208AKV is low voltage 2-Mbit static RAMs organized
as 262,144-words by 8-bit, fabricated by high-performance 0.25µm
CMOS technology.
The M5M5V208AKV is suitable for memory applications where a
simple interfacing , battery operating and battery backup are the
important design objectives.
The M5M5V208AKV is packaged in 32-pin 8mm x 13.4mm
sTSOP packages which is a high reliability and high density surface
mount device.
PIN CONFIGURATION (TOP VIEW)
A
11
A
9
A
8
A
13
W
S
2
A
15
V
CC
A
17
A
16
A
14
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
OE
A
10
S
1
DQ
8
DQ
7
DQ
6
DQ
5
DQ
4
GND
DQ
3
DQ
2
DQ
1
A
0
A
1
A
2
A
3
M5M5V208AKV
25
24
23
22
21
20
19
18
17
FEATURES
Access
time
(max)
Power supply current
Type name
Active
(max)
stand-by
(max)
M5M5V208AKV-55HI
55ns
35mA
(10MHz)
30µA
(Vcc= 3.6V)
M5M5V208AKV-70HI
70ns
7mA
(1MHz)
0.3µA
(Vcc= 3.0V
TYPICAL)
Outline 32P3K-B(KV)
•
Single 2.7 ~3.6V power supply
•
No clock, No refresh
•
Directly TTL compatible : All inputs and outputs
•
Easy memory expansion and power down by S1,S2
•
Data hold on +2V power supply
•
Three-state outputs : OR - tie capability
•
OE prevents data contention in the I/O bus
•
Common data I/O
•
Package
M5M5V208AKV ············· 32pin 8 X 13.4 mm
2
sTSOP
Rev ision-A0.5
1
RENESAS LSIs
M5M5V208AKV
2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM
FUNCTION
The operation mode of the M5M5V208AKV series are determined by a
combination of the device control inputs S
1
,S
2
,W and OE.
Each mode is summarized in the function table.
A write cycle is executed whenever the low level W overlaps with the low
level S
1
and the high level S
2
. The address must be set up before the
write cycle and must be stable during the entire cycle. The data is
latched into a cell on the trailing edge of W,S
1
or S
2
,whichever occurs
first,requiring the set-up and hold time relative to these edge to be
maintained. The output enable input OE directly controls the output
stage. Setting the OE at a high level, the output stage is in a high-
impedance state, and the data bus contention problem in the write cycle
is eliminated.
A read cycle is executed by setting W at a high level and OE at a low
level while S
1
and S
2
are in an active state(S
1
=L,S
2
=H).
When setting S
1
at a high level or S
2
at a low level, the chip are in a
non-selectable mode in which both reading and writing are disabled. In
this mode, the output stage is in a high- impedance state, allowing OR-
tie with other chips and memory expansion by S
1
and S
2
. The power
supply current is reduced as low as the stand-by current which is
specified as I
CC3
or I
CC4
, and the memory data can be held at +2V power
supply, enabling battery back-up operation during power failure or
power-down operation in the non-selected mode.
FUNCTION TABLE
S
1
X
H
L
L
L
S
2
L
X
H
H
H
W
X
X
L
H
H
OE
Mode
DQ
X Non selection High-impedance
X Non selection High-impedance
Din
X
Write
Dout
L
Read
High-impedance
H
I
CC
Stand-by
Stand-by
Active
Active
Active
Note 1: "H" and "L" in this table mean VIH and VIL, respectively.
2: "X" in this table should be "H" or "L".
BLOCK DIAGRAM
A2 18
A3 17
A4 16
A5 15
A6 14
A7 13
A12 12
A14 11
A16 10
A17 9
21 DQ1
22 DQ2
262144 WORDS
X 8 BITS
( 1024 ROWS
X256 COLUMNS
X 8 BLOCKS )
23 DQ3
25 DQ4
26 DQ5
27 DQ6
28 DQ7
29 DQ8
DATA
INPUTS/
OUTPUTS
ADDRESS
INPUTS
A15
A13
7
4
CLOCK
GENERATOR
A8 3
A9
2
5
WRITE
W CONTROL
INPUT
CHIP
SELECT
INPUTS
A11 1
A1 19
A0 20
A10 31
30 S1
6
S2
OUTPUT
32 OE ENABLE
INPUT
8
24
V
CC
GND
(0V)
Rev ision-A0.5
2
RENESAS LSIs
M5M5V208AKV
2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc
V
I
V
O
P
d
T
opr
T
stg
Supply voltage
Input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature
Parameter
Conditions
Ratings
- 0.5*~4.6
- 0.5*~Vcc + 0.3
0~Vcc
700
- 40~85
- 65~150
Unit
V
V
V
mW
°C
°C
With respect to GND
Ta=25°C
* -3.0V in case of AC ( Pulse width
≤
30ns )
DC ELECTRICAL CHARACTERISTICS
(Ta= -40~85°C, Vcc=2.7~3.6V, unless otherwise noted)
Symbol
V
IH
V
IL
V
OH1
V
OH2
V
OL
I
I
I
O
I
CC1
Parameter
High-level input voltage
Low-level input voltage
High-level output voltage 1
High-level output voltage 2
Low-level output voltage
Input current
Output current in off-state
Active supply current
(CMOS-level input)
Active supply current
(TTL-level input)
I
OH
= - 0.5mA
I
OH
= - 0.05mA
I
OL
= 2mA
V
I
=0~Vcc
S
1
=V
IH
or S
2
=V
IL
or OE=V
IH
V
I/O
=0~V
CC
S
1
≤
0.2V,S
2
≥
Vcc-0.2V
other inputs
≤
0.2V or
≥
Vcc-0.2V
,
Output-open
S
1
=V
IL
,S
2
=V
IH
,
other inputs=V
IH
or V
IL,
Output-open
10MHz
1MHz
10MHz
1MHz
~25°C
I
CC3
Stand-by current
1) S
2
≤
0.2V, other inputs=0 ~ V
CC
2) S
1
≥
V
CC
- 0.2V, S
2
≥
V
CC
- 0.2V
other inputs=0 ~ V
CC
~40°C
~70°C
~85°C
I
CC4
Stand-by current
1) S
1
=V
IH,
other inputs=V
IL or
V
IH
2) S
2
=V
IL
, other inputs=V
IL or
V
IH
28
5
33
5
0.3
Test conditions
Limits
Min
2.0
-0.3*
2.4
Vcc
- 0.5
0.4
±1
±1
30
7
35
7
2
5
10
30
0.33
mA
µA
mA
mA
Typ
Max
Vcc
+ 0.3
0.6
Unit
V
V
V
V
V
µA
µA
I
CC2
* -3.0V in case of AC ( Pulse width
≤
30ns )
CAPACITANCE
(Ta=- 40~85°C, unless otherwise noted)
Symbol
C
I
C
O
Parameter
Input capacitance
Output capacitance
Test conditions
V
I
=GND, V
I
=25mVrms, f=1MHz
V
O
=GND,V
O
=25mVrms, f=1MHz
Limits
Typ
Unit
pF
pF
Min
Max
8
10
Note 3: Direction for current flowing into an IC is positive (no mark).
4: T ypical value is Vcc = 3V, Ta = 25
°C
Rev ision-A0.5
3
RENESAS LSIs
M5M5V208AKV
2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS
(Ta=- 40~85°C, unless otherwise noted )
(1) MEASUREMENT CONDITIONS
V
CC
.................................
Input pulse level .............
.....
Input rise and fall time
Reference level...............
Output loads...................
2.7~3.6V
V
IH
=2.2V,V
IL
=0.4V
5ns
V
OH
=V
OL
=1.5V
Fig.1, C
L
=30pF
C
L
=5pF (for t
en
,t
dis
)
Transition is measured ± 500mV from steady
state voltage. (for t
en
,t
dis
)
DQ
C
L
including
scope and JIG
1TTL
Fig.1 Output load
(2) READ CYCLE
Limits
Symbol
t
CR
t
a(A)
t
a(S1)
t
a(S2)
t
a(OE)
t
dis(S1)
t
dis(S2)
t
dis(OE)
t
en(S1)
t
en(S2)
t
en(OE)
t
V(A)
Read cycle time
Address access time
Chip select 1 access time
Chip select 2 access time
Output enable access time
Output disable time after S
1
high
Output disable time after S
2
low
Output disable time after OE high
Output enable time after S
1
low
Output enable time after S
2
high
Output enable time after OE low
Data valid time after address
Parameter
-55HI
Max
Min
55
55
55
55
30
20
20
20
10
10
5
10
10
10
5
10
-70HI
Max
Min
70
70
70
70
35
25
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(3) WRITE CYCLE
Limits
Symbol
t
CW
t
w(W)
t
su(A)
t
su(A-WH)
t
su(S1)
t
su(S2)
t
su(D)
t
h(D)
t
rec(W)
t
dis(W)
t
dis(OE)
t
en(W)
t
en(OE)
Parameter
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to W
Chip select 1 setup time
Chip select 2 setup time
Data setup time
Data hold time
Write recovery time
Output disable time from W low
Output disable time from OE high
Output enable time from W high
Output enable time from OE low
-55HI
Min
Max
55
45
0
50
50
50
25
0
0
20
20
5
5
5
5
-70HI
Min
Max
70
55
0
65
65
65
30
0
0
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev ision-A0.5
4
RENESAS LSIs
M5M5V208AKV
2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM
(4) TIMING DIAGRAMS
Read cycle
t
CR
A
0~ 17
t
a(A)
t
v (A)
t
a (S1)
S
1
(Note 5)
(Note 5)
t
dis (S1)
S
2
(Note 5)
t
a (S2)
t
a (OE)
t
en (OE)
t
dis (S2)
(Note 5)
OE
(Note 5)
t
dis (OE)
t
en (S1)
t
en (S2)
(Note 5)
DQ
1~ 8
W = "H" level
DATA VALID
Write cycle (W control mode)
t
CW
A
0~ 17
t
su (S1)
S
1
(Note 5)
(Note 5)
S
2
(Note 5)
t
su (S2)
(Note 5)
t
su (A-WH)
OE
t
su (A)
W
t
w (W)
t
rec (W)
t
dis (W)
t
dis (OE)
DQ
1~ 8
t
en (W)
DATA IN
STABLE
t
su (D)
t
h (D)
t
en(OE)
Rev ision-A0.5
5
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