W83627SF Data Sheet Revision History
Pages
1
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n.a.
All
Dates
2000/09/17
2000/11/15
Version
0.50
0.60
Version
on Web
Main Contents
First published
New composition
Please note that all data and specifications are subject to change without notice. All the
trade marks of products and companies mentioned in this data sheet belong to their
respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems
where malfunction of these products can reasonably be expected to result in personal
injury. Winbond customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Winbond for any damages resulting
from such improper use or sales.
W83627SF
PRELIM INARY
TABLE OF CONTENTS
GENERAL DESCRIPTION ---------------------------------------------------------------------------------- 1
PIN CONFIGURATION FOR W83627SF---------------------------------------------------------------- 6
1. PIN DESCRIPTION------------------------------------------------------------------------------------------------------------------------- 7
1.1 LPC INTERFACE -------------------------------------------------------------------------------------------------------------------------- 7
1.2 FDC INTERFACE-------------------------------------------------------------------------------------------------------------------------- 8
1.3 MULTI-MODE PARALLEL PORT ---------------------------------------------------------------------------------------------------- 9
1.4 SERIAL PORT INTERFACE ------------------------------------------------------------------------------------------------------------ 13
1.5 KBC INTERFACE-------------------------------------------------------------------------------------------------------------------------- 15
1.6 ACPI INTERFACE------------------------------------------------------------------------------------------------------------------------- 15
1.7 GAME PORT & MIDI PORT------------------------------------------------------------------------------------------------------------ 16
1.8 GENERAL PURPOSE I/O PORT-------------------------------------------------------------------------------------------------------- 17
1.8.1 General Purpose I/O Port 1 (Power source is Vcc)------------------------------------------------------------------------ 17
1.8.2 General Purpose I/O Port 2 (Power source is Vcc)------------------------------------------------------------------------ 17
1.8.3 General Purpose I/O Port 3 (Power souce is VSB) ------------------------------------------------------------------------ 18
1.9 SMART CARD INTERFACE AND GENERAL PURPOSE I/O PORT 7 (POWERED BY VCC EXCEPT
SCPSNT# WHICH IS POWERED BY VSB)---------------------------------------------------------------------------------------------- 19
1.10 GENERAL PURPOSE I/O PORT 4 (POWERED BY GP4PWR) ---------------------------------------------------------------- 20
1.11 GENERAL PURPOSE I/O PORT 5, 6 (POWERED BY VCC)-------------------------------------------------------------------- 20
1.12 32KHZ CRYSTAL OSCILLATOR---------------------------------------------------------------------------------------------------- 21
1.13 POWER PINS------------------------------------------------------------------------------------------------------------------------------ 21
2. LPC (LOW PIN COUNT) INTERFACE---------------------------------------------------------------- 22
3. FDC FUNCTIONAL DESCRIPTION ------------------------------------------------------------------ 23
3.1 W83627SF FDC----------------------------------------------------------------------------------------------------------------------------- 23
3.1.1 AT interface--------------------------------------------------------------------------------------------------------------------------- 23
3.1.2 FIFO (Data) -------------------------------------------------------------------------------------------------------------------------- 23
3.1.3 Data Separator ---------------------------------------------------------------------------------------------------------------------- 24
Publication Release Date: Nov. 2000
Preliminary Revision 0.60
-I -
W83627SF
PRELIM INARY
3.1.4 Write Precompensation------------------------------------------------------------------------------------------------------------ 25
3.1.5 Perpendicular Recording Mode ------------------------------------------------------------------------------------------------ 25
3.1.6 FDC Core ----------------------------------------------------------------------------------------------------------------------------- 25
3.1.7 FDC Commands--------------------------------------------------------------------------------------------------------------------- 25
3.2 REGISTER DESCRIPTIONS------------------------------------------------------------------------------------------------------------- 36
3.2.1 Status Register A (SA Register) (Read base address + 0) --------------------------------------------------------------- 36
3.2.2 Status Register B (SB Register) (Read base address + 1) --------------------------------------------------------------- 38
3.2.3 Digital Output Register (DO Register) (Write base address + 2) ----------------------------------------------------- 40
3.2.4 Tape Drive Register (TD Register) (Read base address + 3) ----------------------------------------------------------- 40
3.2.5 Main Status Register (MS Register) (Read base address + 4) --------------------------------------------------------- 41
3.2.6 Data Rate Register (DR Register) (Write base address + 4)------------------------------------------------------------ 41
3.2.7 FIFO Register (R/W base address + 5)---------------------------------------------------------------------------------------- 43
3.2.8 Digital Input Register (DI Register) (Read base address + 7) --------------------------------------------------------- 45
3.2.9 Configuration Control Register (CC Register) (Write base address + 7) ------------------------------------------ 46
4. UART PORT--------------------------------------------------------------------------------------------------- 47
4.1 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A, UART B) ------------------------------------ 47
4.2 REGISTER ADDRESS -------------------------------------------------------------------------------------------------------------------- 47
4.2.1 UART Control Register (UCR) (Read/Write)-------------------------------------------------------------------------------- 47
4.2.2 UART Status Register (USR) (Read/Write) ---------------------------------------------------------------------------------- 50
4.2.3 Handshake Control Register (HCR) (Read/Write) ------------------------------------------------------------------------ 51
4.2.4 Handshake Status Register (HSR) (Read/Write)--------------------------------------------------------------------------- 52
4.2.5 UART FIFO Control Register (UFR) (Write only) ------------------------------------------------------------------------- 53
4.2.6 Interrupt Status Register (ISR) (Read only)--------------------------------------------------------------------------------- 54
4.2.7 Interrupt Control Register (ICR) (Read/Write)----------------------------------------------------------------------------- 55
4.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write) -------------------------------------------------------------- 55
4.2.9 User-defined Register (UDR) (Read/Write)---------------------------------------------------------------------------------- 56
5. CIR RECEIVER PORT------------------------------------------------------------------------------------- 57
5.1 CIR REGISTERS---------------------------------------------------------------------------------------------------------------------------- 57
5.1.1 Bank0.Reg0 - Receiver Buffer Registers (RBR) (Read)------------------------------------------------------------------- 57
5.1.2 Bank0.Reg1 - Interrupt Control Register (ICR) ---------------------------------------------------------------------------- 57
5.1.3 Bank0.Reg2 - Interrupt Status Register (ISR)------------------------------------------------------------------------------- 57
5.1.4 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3) --------------------- 58
5.1.5 Bank0.Reg4 - CIR Control Register (CTR) ---------------------------------------------------------------------------------- 58
5.1.6 Bank0.Reg5 - UART Line Status Register (USR) -------------------------------------------------------------------------- 59
5.1.7 Bank0.Reg6 - Remote Infrared Config Register (RIR_CFG) ------------------------------------------------------------ 60
Publication Release Date: Nov. 2000
Revision 0.60
-II -
W83627SF
PRELIM INARY
5.1.8 Bank0.Reg7 - User Defined Register (UDR/AUDR) ----------------------------------------------------------------------- 61
5.1.9 Bank1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL) ------------------------------------------------------------------- 62
5.1.10 Bank1.Reg2 - Version ID Regiister I (VID)--------------------------------------------------------------------------------- 63
5.1.11 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3)-------------------- 63
5.1.12 Bank1.Reg4 - Timer Low Byte Register (TMRL) -------------------------------------------------------------------------- 63
5.1.13 Bank1.Reg5 - Timer High Byte Register (TMRH) ------------------------------------------------------------------------ 63
6. PARALLEL PORT ------------------------------------------------------------------------------------------ 64
6.1 PRINTER INTERFACE LOGIC --------------------------------------------------------------------------------------------------------- 64
6.2 ENHANCED PARALLEL PORT (EPP) ----------------------------------------------------------------------------------------------- 65
6.2.1 Data Swapper------------------------------------------------------------------------------------------------------------------------ 66
6.2.2 Printer Status Buffer---------------------------------------------------------------------------------------------------------------- 66
6.2.3 Printer Control Latch and Printer Control Swapper--------------------------------------------------------------------- 67
6.2.4 EPP Address Port ------------------------------------------------------------------------------------------------------------------- 67
6.2.5 EPP Data Port 0-3 ------------------------------------------------------------------------------------------------------------------ 68
6.2.6 Bit Map of Parallel Port and EPP Registers -------------------------------------------------------------------------------- 68
6.2.7 EPP Pin Descriptions-------------------------------------------------------------------------------------------------------------- 69
6.2.8 EPP Operation----------------------------------------------------------------------------------------------------------------------- 69
6.3 EXTENDED CAPABILITIES PARALLEL (ECP) PORT -------------------------------------------------------------------------- 70
6.3.1 ECP Register and Mode Definitions------------------------------------------------------------------------------------------- 70
6.3.2 Data and ecpAFifo Port----------------------------------------------------------------------------------------------------------- 71
6.3.3 Device Status Register (DSR)---------------------------------------------------------------------------------------------------- 71
6.3.4 Device Control Register (DCR) ------------------------------------------------------------------------------------------------- 72
6.3.5 cFifo (Parallel Port Data FIFO) Mode = 010 ------------------------------------------------------------------------------ 73
6.3.6 ecpDFifo (ECP Data FIFO) Mode = 011 ------------------------------------------------------------------------------------ 73
6.3.7 tFifo (Test FIFO Mode) Mode = 110 ------------------------------------------------------------------------------------------ 73
6.3.8 cnfgA (Configuration Register A) Mode = 111----------------------------------------------------------------------------- 73
6.3.9 cnfgB (Configuration Register B) Mode = 111----------------------------------------------------------------------------- 73
6.3.10 ecr (Extended Control Register) Mode = all ------------------------------------------------------------------------------ 74
6.3.11 Bit Map of ECP Port Registers ------------------------------------------------------------------------------------------------ 75
6.3.12 ECP Pin Descriptions------------------------------------------------------------------------------------------------------------ 76
6.3.13 ECP Operation--------------------------------------------------------------------------------------------------------------------- 77
6.3.14 FIFO Operation-------------------------------------------------------------------------------------------------------------------- 77
6.3.15 DMA Transfers --------------------------------------------------------------------------------------------------------------------- 78
6.3.16 Programmed I/O (NON-DMA) Mode----------------------------------------------------------------------------------------- 78
6.4 EXTENSION FDD MODE (EXTFDD) ------------------------------------------------------------------------------------------------ 78
-III -
Publication Release Date: Nov. 2000
Revision 0.60
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