Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: DSP56303VF100, DSP56303VL100
PIO_EB
Table of Contents
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: DSP56303VF100, DSP56303VL100
Data Sheet Conventions .......................................................................................................................................ii
Target Applications ............................................................................................................................................. iv
Power ................................................................................................................................................................1-3
External Memory Expansion Port (Port A) ......................................................................................................1-4
Interrupt and Mode Control ..............................................................................................................................1-7
JTAG and OnCE Interface ..............................................................................................................................1-16
Maximum Ratings.............................................................................................................................................2-1
DC Electrical Characteristics............................................................................................................................2-2
AC Electrical Characteristics............................................................................................................................2-3
expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts
• Direct memory access (DMA) with six DMA channels supporting internal and external accesses; one-, two-
, and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and
triggering from interrupt lines and all peripherals
• Phase-lock loop (PLL) allows change of low-power divide factor (DF) without loss of lock and output clock
with skew elimination
• Hardware debugging support including on-chip emulation (OnCE‘) module, Joint Test Action Group (JTAG)
test access port (TAP)
• Enhanced 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides
glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs
• Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows
six-channel home theater)
• Serial communications interface (SCI) with baud rate generator
• Triple timer module
• Up to thirty-four programmable general-purpose input/output (GPIO) pins, depending on which peripherals
are enabled
• 192
×
24-bit bootstrap ROM
• 8 K
×
24-bit RAM total
• Program RAM, instruction cache, X data RAM, and Y data RAM sizes are programmable:
High-Performance
DSP56300 Core
Internal Peripherals
Internal Memories
Program RAM
Size
4096
×
24-bit
3072
×
24-bit
2048
×
24-bit
1024
×
24-bit
Instruction
Cache Size
0
1024
×
24-bit
0
1024
×
24-bit
X Data RAM
Size
2048
×
24-bit
2048
×
24-bit
3072
×
24-bit
3072
×
24-bit
Y Data RAM
Size
2048
×
24-bit
2048
×
24-bit
3072
×
24-bit
3072
×
24-bit
Instruction
Cache
disabled
enabled
disabled
enabled
Switch Mode
disabled
disabled
enabled
enabled
External Memory
Expansion
• Data memory expansion to two 256 K
×
24-bit word memory spaces using the standard external address
lines
• Program memory expansion to one 256 K
×
24-bit words memory space using the standard external
address lines
• External memory expansion port
• Chip select logic for glueless interface to static random access memory (SRAMs)
• Internal DRAM Controller for glueless interface to dynamic random access memory (DRAMs)
•
•
•
•
Very low-power CMOS design
Wait and Stop low-power standby modes
Fully static design specified to operate down to 0 Hz (dc)
Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-
dependent)
Power Dissipation
Packaging
• 144-pin TQFP package in lead-free or lead-bearing versions
• 196-pin molded array plastic-ball grid array (MAP-BGA) package in lead-free or lead-bearing versions
DSP56303 Technical Data, Rev. 11
Freescale Semiconductor
iii
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: DSP56303VF100, DSP56303VL100
Target Applications
Examples include:
•
•
•
•
Multi-line voice/data/fax processing
Video conferencing
Audio applications
Control
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: DSP56303VF100, DSP56303VL100
Product Documentation
The documents listed in
Table 2
are required for a complete description of the DSP56303 device and are necessary
to design properly with the part. Documentation is available from a local Freescale distributor, a Freescale
semiconductor sales office, or a Freescale Semiconductor Literature Distribution Center. For documentation
updates, visit the Freescale DSP website. See the contact information on the back cover of this document.
Table 2.
DSP56303 Documentation
Name
DSP56303
User’s Manual
Description
Detailed functional description of the DSP56303 memory configuration,
operation, and register programming
Order Number
DSP56303UM
DSP56300FM
See the DSP56303 product website
DSP56300 Family
Detailed description of the DSP56300 family processor core and instruction set
Manual
Application Notes
Documents describing specific applications or optimized device operation
including code examples
DSP56303 Technical Data, Rev. 11
iv
Freescale Semiconductor
Signals/Connections
1
The DSP56303 input and output signals are organized into functional groups as shown in
Table 1-1. Figure 1-1
diagrams the DSP56303 signals by functional group. The remainder of this chapter describes the signal pins in
each functional group.
Table 1-1.
DSP56303 Functional Signal Groupings
Number of Signals
Functional Group
TQFP
Power (V
CC
)
Ground (GND)
Clock
PLL
Address bus
Data bus
Bus control
Interrupt and mode control
Host interface (HI08)
Enhanced synchronous serial interface (ESSI)
Serial communication interface (SCI)
Timer
OnCE/JTAG Port
Notes:
1.
2.
3.
4.
5.
Port B
2
Ports C and D
3
Port E
4
Port A
1
18
19
2
3
18
24
13
5
16
12
3
3
6
MAP-BGA
18
66
2
3
18
24
13
5
16
12
3
3
6
Port A signals define the external memory interface port, including the external address bus, data bus, and control signals.
Port B signals are the HI08 port signals multiplexed with the GPIO signals.
Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals.
Port E signals are the SCI port signals multiplexed with the GPIO signals.
There are 2 signal connections in the TQFP package and 7 signal connections in the MAP-BGA package that are not used.
These are designated as no connect (NC) in the package description (see
Chapter 3).
Note:
This chapter refers to a number of configuration registers used to select individual multiplexed signal
functionality. Refer to the
DSP56303 User’s Manual
for details on these configuration registers.
DSP56303 Technical Data, Rev. 11
Freescale Semiconductor
1-1
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: DSP56303VF100, DSP56303VL100
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