8N3QV01BG-1153CDI8 datasheet, PDF

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8N3QV01BG-1153CDI8: DescriptionLVPECL Output Clock Oscillator; CategoryPassive components oscillator; File Size229KB，22 Pages; ManufacturerIDT (Integrated Device Technology)

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8N3QV01BG-1153CDI8 Overview

LVPECL Output Clock Oscillator

8N3QV01BG-1153CDI8 Parametric

Parameter Name	Attribute value
Maker	IDT (Integrated Device Technology)
Reach Compliance Code	compli
Manufacturer's serial number	IDT8N3QV01
Oscillator type	LVPECL
Base Number Matches	1

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Quad-Frequency Programmable

VCXO

IDT8N3QV01 Rev G

DATA SHEET

General Description

The IDT8N3QV01 is a Quad-Frequency Programmable VCXO with

very flexible frequency and pull-range programming capabilities.

The device uses IDT’s fourth generation FemtoClock® NG

technology for an optimum of high clock frequency and low phase

noise performance. The device accepts 2.5V or 3.3V supply and is

packaged in a small, lead-free (RoHS 6) 10-lead Ceramic 5mm x

7mm x 1.55mm package.

Besides the 4 default power-up frequencies set by the FSEL0 and

FSEL1 pins, the IDT8N3QV01 can be programmed via the I

interface to any output clock frequency between 15.476MHz to

866.67MHz and from 975MHz to 1,300MHz to a very high degree of

precision with a frequency step size of 435.9Hz ÷N (N is the PLL

output divider). Since the FSEL0 and FSEL1 pins are mapped to 4

independent PLL M and N divider registers (P, MINT, MFRAC and

N), reprogramming those registers to other frequencies under

control of FSEL0 and FSEL1 is supported. The extended

temperature range supports wireless infrastructure, tele-

communication and networking end equipment requirements. The

device is a member of the high-performance clock family from IDT.

Features

•

Fourth generation FemtoClock® NG technology

Programmable clock output frequency from 15.476MHz to

866.67MHz and from 975MHz to 1,300MHz

Four power-up default frequencies (see part number order

codes), reprogrammable by I

C programming interface for the output clock frequency, APR

and internal PLL control registers

Frequency programming resolution is 435.9Hz ÷N

Absolute pull-range (APR) programmable from ±4.5 to

±754.5ppm

One 2.5V or 3.3V LVPECL differential clock output

Two control inputs for the power-up default frequency

LVCMOS/LVTTL compatible control inputs

RMS phase jitter @ 156.25MHz (12kHz - 20MHz):



0.487ps (typical)

RMS phase jitter @ 156.25MHz (1kHz - 40MHz):



0.614ps (typical)

2.5V or 3.3V supply voltage modes

-40°C to 85°C ambient operating temperature

Available in Lead-free (RoHS 6) package

Block Diagram

OSC

114.285 MHz

÷MINT,

MFRAC

FSEL1

FSEL0

SCLK

SDATA

Pulldown

Pullup

Pin Assignment

÷P

PFD

LPF

FemtoClock® NG

VCO

1950-2600MHz

÷N

Q

SDATA

SCLK

VC 1

OE 2

FSEL0

A/D

Configuration Register (ROM)

(Frequency, APR, Polarity)

C Control

IDT8N3QV01 Rev G

10-lead Ceramic 5mm x 7mm x 1.55mm

package body

CD Package

Top View

IDT8N3QV01GCD REVISION A

FEBRUARY 24, 2012

FSEL1

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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