Acoustic noise-less 3.0kW/AC400V Class 3 Phase inverter and other motor control applica-
tions.
PACKAGE OUTLINES
56
±
0.8
15.5
4-R2
4-φ4.5
MOUNTING
HOLE
20.4
±
1
Terminals Assignment:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CBU+
CBU–
CBV+
CBV–
CBW+
CBW–
GND
VDL
VDH
CL
FO1
FO2
FO3
CU
CV
CW
UP
VP
WP
UN
VN
WN
Br
31
32
33
34
35
36
P
B
N
U
V
W
10
0.5
1
7
23
5
2
±
0.3
6
±
0.3
(22)
0.5
4-R5
5
4-
φ
41
±
0.5
15.5
60
±
0.5
1
±
0.3
76
±
1
50
32
15.5
5
V
3
(102)
3
31
5
1
36
10
12.7
±
0.3
63.5
±
0.8
105
±
0.5
115
±
1
96
2.5
17.5
63
±
0.8
4-φ3.2
3
17
±
0.8
LABEL
(Fig. 1)
8.5
13
Jan. 2000
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
tion. hange.
cifica
c
al spe ubject to
a fin
s
is not limits are
is ric
e: Th
t
Notice parame
m
So
PR
Y
INAR
ELIM
PS12017-A
FLAT-BASE TYPE
INSULATED TYPE
CBU+
CBU–
Application Specific Intelligent
Power Module
Protection
Circuit
P
Input Circuit
Drive Circuit
Brake resistor connection,
Inrush prevention circuit,
etc.
AC 400V line input
R
S
T
Photo
Coupler
B
CBV+
CBV–
INTERNAL FUNCTIONS BLOCK DIAGRAM
CBW+
CBW–
U
V
W
M
Z
C
N
T
S
AC 400V
line output
Z : Surge absorber.
C : AC filter (Ceramic condenser 2.2~6.5nF)
[Note : Additionally an appropriate Line-to line
surge absorber circuit may become necessary
depending on the application environment].
Current sensing
circuit
Input signal conditioning
U
P
V
P
W
P
U
N
V
N
W
N
B
r
Drive Circuit
Fo Logic
Protection
circuit
Control supply
fault sense
GND
VDL VDH
CU CV CW
CL,FO
1
,FO
2
,FO
3
Fault output
Analogue signal output corresponding to
PWM input
(5V line) Note 3)
each phase current (5V line) Note 1) (5V line) Note 2)
Note 1) To prevent chances of signal oscillation, a series resistor (1kΩ) coupling at each output is recommended.
Note 2) By virtue of integrating a photo-coupler inside the module, direct coupling to CPU, without any extemal opto or transformer isolation is possible.
Note 3) All outputs are open collector type. Each signal line should be pulled up to plus side of the 5V power supply with approximately 5.1kΩ resistance.
Note 4) The wiring between power DC link capacitor and P/N terminals should be as short as possible to protect the ASIPM against catastrophic high surge voltage.
For extra precaution, a small film snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to these P and N DC power input pins.
(Fig. 2)
MAXIMUM RATINGS
(Tj = 25°C)
INVERTER PART (Including Brake Part)
Symbol
V
CC
Item
Supply voltage
Condition
Applied between P-N
Ratings
900
1000
1200
1200
±25
(±50)
10 (20)
)” means I
C
peak value
10 (20)
Unit
V
V
V
V
A
A
A
V
CC(surge)
Supply voltage (surge)
Applied between P-N, Surge-value
V
P
or V
N
Each output IGBT collector-emitter static voltage Applied between P-U, V, W, Br or U, V, W, Br-N
V
P(S)
or
Each output IGBT collector-emitter surge voltage Applied between P-U, V, W, Br or U, V, W, Br-N
V
N(S)
±Ic(±Icp)
Ic(Icp)
I
F
(I
FP
)
Each output IGBT collector current
Brake IGBT collector current
Brake diode anode current
T
C
= 25°C
Note : “(
CONTROL PART
Symbol
V
DH
, V
DB
V
DL
V
CIN
V
FO
I
FO
V
CL
I
CL
I
CO
Supply voltage
Supply voltage
Input signal voltage
Fault output supply voltage
Fault output current
Current-limit warning output voltage
CL output current
Analogue-current-signal output current
Item
Condition
Applied between V
DH
-GND, C
BU+
-C
BU–
,
C
BV+
-C
BV–
, C
BW+
-C
BW–
Applied between V
DL
-GND
Applied between U
P
· V
P
· W
P
· U
N
· V
N
·
W
N
· B
r
-GND
Applied between F
O1
· F
O2
· F
O3
-GND
Sink current of F
O1
· F
O2
· F
O3
Applied between CL-GND
Sink current of CL
Sink current of CU · CV · CW
Ratings
20
7
–0.5 ~ V
DL
+0.5
–0.5 ~ 7
15
–0.5 ~ 7
15
±1
Unit
V
V
V
V
mA
V
mA
mA
Jan. 2000
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PRE
n.
.
ificatio hange
l spec ct to c
a finaare subje
ot
is is nic limits
e: Th
tr
Notice parame
Som
Y
INAR
LIM
PS12017-A
FLAT-BASE TYPE
INSULATED TYPE
TOTAL SYSTEM
Symbol
T
j
T
stg
T
C
V
ISO
—
Item
Junction temperature
Storage temperature
Module case operating temperature
Isolation voltage
Mounting torque
Condition
(Note 2)
—
(Fig. 3)
60 Hz sinusoidal AC for 1 minute, between all terminals
and base plate.
Mounting screw: M4.0
Ratings
–20 ~ +125
–40 ~ +125
–20 ~ +100
2500
0.98 ~ 1.47
Unit
°C
°C
°C
Vrms
N·m
Note 2) : The item defines the maximum junction temperature for the power elements (IGBT/Diode) of the ASIPM to ensure safe operation.
However, these power elements can endure instantaneous junction temperature as high as 150°C. To make use of this additional
temperature allowance, a detailed study of the exact application conditions is required and, accordingly, necessary information is
to be provided before use.
CASE TEMPERATURE MEASUREMENT POINT (3mm from the base surface)
LABEL
Tc
(Fig. 3)
THERMAL RESISTANCE
Symbol
R
th(jc
)
Q
R
th(jc)F
R
th(jc
)
QB
R
th(jc)FB
R
th(c-f)
Junction to case Thermal
Resistance
Contact Thermal Resistance
Item
Condition
Inverter IGBT (1/6)
Inverter FWDi (1/6)
Brake IGBT
Brake FWDi
Case to fin, thermal grease applied (1 Module)
Ratings
Min.
—
—
—
—
—
Typ.
—
—
—
—
—
Max.
1.6
3.0
2.9
5.5
0.031
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
ELECTRICAL CHARACTERISTICS
(Tj = 25°C, V
DH
= 15V , V
DB
= 15V, V
DL
= 5V unless otherwise noted)
Symbol
V
CE(sat)
V
EC
V
CE(sat)Br
V
FBr
ton
tc(on)
toff
tc(off)
trr
Item
Collector-emitter saturation
voltage
FWDi forward voltage
Condition
V
DL
= 5V, V
DH
= V
DB
= 15V Input = ON,
Tj = 25°C, Ic = 25A
Tj = 25°C, Ic = –25A, Input = OFF
Min.
—
—
—
—
0.40
—
—
—
—
Ratings
Typ.
—
—
—
—
1.4
0.60
2.2
0.9
0.2
Max.
3.6
3.5
3.6
3.5
2.5
1.5
4.0
1.6
—
Unit
V
V
V
V
µs
µs
µs
µs
µs
Brake IGBT
V
DL
= 5V, V
DH
= 15V Input = ON, Tj = 25°C, Ic = 10A
Collector-emitter saturation voltage
Brake diode forward voltage
Tj = 25°C, I
F
= 10A, Input = OFF
1/2 Bridge inductive, Input = ON
Switching times
V
CC
= 600V, Ic = 25A, Tj = 125°C
V
DL
= 5V, V
DH
= 15V, V
DB
= 15V
Note : ton, toff include delay time of the internal control
circuit.
FWD reverse recovery time
V
CC
≤
800V, Input = ON (One-Shot)
Short circuit endurance
(Output, Arm, and Load, Short Tj = 125°C start
Circuit Modes)
13.5V
≤
V
DH
= V
DB
=
≤
16.5V, V
DL
= 5V
V
CC
≤
800V, Tj
≤
125°C,
Switching SOA
I
DH
I
DL
V
th(on)
V
th(off)
R
i
V
DH
Circuit Current
V
DL
Circuit Current
Input on threshold voltage
Input off threshold voltage
Input pull-up resistor
Ic < I
OL
(CL) operation level, Input = ON,
13.5V
≤
V
DH
= V
DB
=
≤
16.5V, V
DL
= 5V
V
DL
= 5V, V
DH
= 15V, V
CIN
= 5V
V
DL
= 5V, V
DH
= 15V, V
CIN
= 5V
• No destruction
• F
O
output by protection operation
• No destruction
• No protecting operation
• No F
O
output
—
—
—
—
0.8
1.4
3.0
150
2.5
—
150
50
2.0
4.0
—
mA
mA
V
V
kΩ
Jan. 2000
Integrated between input terminal-V
DH
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
tion. hange.
cifica
c
al spe ubject to
a fin
s
is not limits are
is ric
e: Th
t
Notice parame
m
So
PR
Y
INAR
ELIM
PS12017-A
FLAT-BASE TYPE
INSULATED TYPE
ELECTRICAL CHARACTERISTICS
(Tj = 25°C, V
DH
= 15V, V
DB
= 15V, V
DL
= 5V unless otherwise noted)
Symbol
f
PWM
t
xx
t
dead
t
int
V
CO
V
C+(200%)
V
C–(200%)
|∆V
CO
|
V
C+
V
C–
∆V
C
(200%)
r
CH
t
d(read)
I
CL(H)
I
CL(L)
±I
OL
SC
OT
OTr
UV
DB
UV
DBr
UV
DH
UV
DHr
OV
DH
OV
DHr
t
dv
I
FO(H)
I
FO(L)
Item
PWM input frequency
Allowable input on-pulse width
Allowable input signal dead time
for blocking arm shoot-through
Input inter-lock sensing
Analogue signal linearity with
output current
Condition
T
C
≤
100°C, Tj
≤
125°C
Note 3)
V
DH
= 15V, V
DL
= 5V, T
C
= –20°C ~ +100°C
Relates to corresponding inputs (Except brake part)
T
C
= –20°C ~ +100°C
Relates to corresponding inputs (Except brake part)
V
DH
= 15V
Ic = 0A
Ic = I
OP(200%)
Ic = –I
OP(200%)
V
DL
= 5V
T
C
= –20 ~ 100°C
(Fig.4)
Min.
—
1
4.0
—
1.87
0.77
2.97
—
(Fig. 4)
—
4.0
—
–5
—
—
—
(Note 4)
(Fig. 7), (Note 5)
20.4
33.6
100
—
10.0
10.5
11.05
11.55
18.00
16.50
—
—
—
Ratings
Typ.
—
—
—
65
2.27
1.17
3.37
15
—
—
1.1
—
3
—
1
25.5
43.0
110
90
11.0
11.5
12.00
12.50
19.20
17.50
10
—
1
Max.
15
500
—
100
2.57
1.47
3.67
—
0.7
—
—
5
—
1
—
30.5
—
120
—
12.0
12.5
12.75
13.25
20.15
18.65
—
1
—
Unit
kHz
µs
µs
ns
V
V
V
mV
V
V
V
%
µs
µA
mA
A
A
°C
°C
V
V
V
V
V
V
µs
µA
mA
Offset change area vs temperature V
DH
= 15V, V
DL
= 5V, T
C
= –20 ~ 100°C
Analogue signal output voltage limit
Analogue signal overall linear
variation
Analogue signal data hold
accuracy
Analogue signal reading time
Signal output cur-
rent of CL operation
Idle
Active
Ic > I
OP(200%)
, V
DH
= 15V,
V
DL
= 5V
|V
CO
-V
C±(200%)
|
Correspond to max. 500µs data hold period only,
Ic = I
OP(200%)
(Fig. 5)
After input signal trigger point
Open collector onput
V
DL
= 5V, V
DH
= 15V, T
C
= –20 ~ 100°C
Tj = 25°C
V
DL
= 5V, V
DH
= 15V
(Fig. 8)
CL warning operation level
Short circuit current trip level
Over tenperature
protection
Trip level
Reset level
Trip level
Reset level
Trip level
Reset level
Trip level
Reset level
Filter time
Fault output current
Idle
Active
Supply circuit
under and
over voltage
protection
T
C
= –20°C ~ +100°C
Tj
≤
125°C
Open collector output
(Note 3) : (a) Allowable minimum input on-pulse width : This item applies to P-side circuit only.
(b) Allowable maximum input on-pulse width : This item applies to both P-side and N-side circuits excluding the brake circuit.
(Note4) : CL output : The "current limit warning (CL) operation circuit outputs warning signal whenever the arm current exceeds this limit. The
circuit is reset automatically by the next input signal and thus, it operates on a pulse-by-pulse scheme.
(Note5) : The short circuit protection works instantaneously when a high short circuit current flows through an internal IGBT rising up momen-
tarily. The protection function is, thus meant primarily to protect the ASIPM against short circuit distraction. Therefore, this function is
not recommended to be used for any system load current regulation or any over load control as this might, cause a failure due to
excessive temperature rise. Instead, the analogue current output feature or the over load warning feature (CL) should be appropri-
ately used for such current regulation or over load control operation. In other words, the PWM signals to the ASIPM should be shut
down, in principle, and not to be restarted before the junction temperature would recover to normal, as soon as a fault is feed back
from its F
O1
pin of the ASIPM indicating a short circuit situation.
RECOMMENDED CONDITIONS
Symbol
V
CC
V
DH
, V
DB
V
DL
Item
Supply voltage
Control supply voltage
Control supply voltage
Condition
Applied between P-N
Applied between V
DH
-GND, C
BU+
-C
BU–
, C
BV+
-C
BV–
,
C
BW+
-C
BW–
Applied between V
DL
-GND
Ratings
Min.
—
13.5
4.8
–1
—
4.8
Using application circuit
Using application circuit
2
4.0
Typ.
600
15.0
5.0
—
—
—
10
—
Max.
800
16.5
5.2
+1
0.3
—
15
—
Unit
V
V
V
V/µs
V
V
kHz
µs
Jan. 2000
∆V
DH
,
∆V
DB
,
Supply voltage ripple
∆V
DL
V
CIN(on)
Input ON voltage
V
CIN(off)
Input OFF voltage
f
PWM
t
dead
PWM Input frequency
Arm shoot-through blocking time
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PRE
n.
.
ificatio hange
l spec ct to c
a finaare subje
ot
is is nic limits
e: Th
tr
Notice parame
Som
Y
INAR
LIM
PS12017-A
FLAT-BASE TYPE
INSULATED TYPE
Fig. 4 OUTPUT CURRENT ANALOGUE SIGNALING
LINEARITY
5
Fig. 5 OUTPUT CURRENT ANALOGUE SIGNALING
“DATA HOLD” DEFINITION
V
C
V
C
–
4
min
max
V
C
–
(200%)
V
DH
=15V
V
DL
=5V
T
C
=
–
20
~
100˚C
500µs
0V
3
V
C0
V
CH
(5
µ
s)
V
CH
(505
µ
s)-V
CH
(5
µ
s)
V
CH
(5
µ
s)
V
CH
(505
µ
s)
V
C
(V)
2
V
C
+(200%)
r
CH
=
1
Analogue output signal
data hold range
V
C
+
0
–400 –300 –200 –100
0
100 200 300 400
Note ; Ringing happens around the point where the signal output
voltage changes state from “analogue” to “data hold” due
to test circuit arrangement and instrumentational trouble.
Therefore, the rate of change is measured at a 5
µs
delayed point.
Real load current peak value.(%)(I
c
=I
o
!
2)
Fig. 6 INPUT INTERLOCK OPERATION TIMING CHART
Input signal V
CIN(p)
of each phase upper arm
Input signal V
CIN(n)
of each phase lower arm
0V
0V
Gate signal V
o(p)
of each phase upper arm
(ASIPM internal)
Gate signal V
o(n)
of each phase upper arm
(ASIPM internal)
Error output F
O1
0V
0V
0V
Note : Input interlock protection circuit ; It is operated when the input signals for any upper-arm / lower-arm pair of a phase are simulta-
neously in “LOW” level.
By this interlocking, both upper and lower IGBTs of this mal-triggered phase are cut off, and “F
O
” signal is outputted. After an “input
interlock” operation the circuit is latched. The “F
O
” is reset by the high-to-low going edge of either an upper-leg, or a lower-leg input,
whichever comes in later.
Fig. 7 TIMING CHART AND SHORT CIRCUIT PROTECTION OPERATION
Input signal V
CIN
of each phase
upper arm
Short circuit sensing signal V
S
0V
0V
S
C
delay time
Gate signal Vo of each phase
upper arm(ASIPM internal)
Error output F
O1
0V
0V
Note : Shor t circuit protection operation. The protection operates with “F
O
” flag and reset on a pulse-by-pulse scheme. The protection by
gate shutdown is given only to the IGBT that senses an overload (excluding the IGBT for the “Brake”).
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