Acoustic noise-less 0.4kW/AC200V class 3 phase inverter and other motor control applica-
tions
PACKAGE OUTLINES
4-R2
0.5
V
6
12 3 4 5 6
7 8 91011121314151617181920212223
Terminals Assignment:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CBU+
CBU–
CBV+
CBV–
CBW+
CBW–
GND
NC
VDH
CL
FO1
FO2
FO3
CU
CV
CW
UP
VP
WP
UN
21 VN
22 WN
23 Br
2424
24
4
2
±
0.3
84.2
±
1
50
2
2-φ4
72
±
0.8
V
0.5
31
32 33 34 35 36 37 38 39 40
1.2
V
Control Pin top
portion details
V
Main terminal top
portion details
0.8
±
0.5
0
24
5.08
±
0.3
!
9 = 45.72
±
0.8
(12.25) 4
4.14
20.4
±
1
27
±
1
V
0.6
2-R4
31
32
33
34
35
36
37
38
39
40
R
S
T
P1
P2
N
B
U
V
W
17.6
±
0.5
3.5
LABEL
54
±
0.5
0.3
0~0.8
0~0.8
8.5
12
0.35MAX
0.4
12
±
0.5
0
0.5
0.6
62
±
1
0.5
±
0.03
(Fig. 1)
Jan. 2000
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11013
FLAT-BASE TYPE
INSULATED TYPE
INTERNAL FUNCTIONS BLOCK DIAGRAM
C3 ; 3.3µF or more, tight tolerance, temp-compensated electrolytic type (Note : the value may change
depending on the type PWM control scheme used in the applied system)
C4 ; 2µF R-category ceramic condenser for noise filtering.
CBW–
CBW+
C4,C3
CBU–
CBU+
CBV–
CBV+
Application Specific Intelligent
Power Module
P2
Brake resistor
connection,
B
Inrush prevention P1
circuit, etc.
AC200V line input
R
S
T
Z
C
N
Z : Surge absorber.
C : AC filter (Ceramic condenser 2.2~6.5nF)
[Note : Additionally an appropriate Line-to line
surge absorber circuit maybe necessary
depending on the application environment].
Protection
Circuit
Level shifter
Drive Circuit
U
V
W
M
T.S.
AC 200V line
output
Current sensing
circuit
Trig signal conditioning
Drive Curcuit
FO Logic
Protection
circuit
Control supply
fault sense
C2
C2 ;
3.3µF or more
GND VDH
(15V line)
Note 1) To prevent chances of signal oscillation, an RC coupling at each output is recommended. (see also Fig.10)
Note 2) By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU, without any opto or transformer isolation ispossible. (see also Fig.10)
Note 3) All these outputs are open collector type. Each signal line should be pulled up to plus side of the 5V power supply with approximately 5.1kΩ resistance. (see also Fig.10)
Note 4) The wiring between power DC link capacitor and P/N terminals should be as short as possible to protect the ASIPM against catastrophic high surge voltage. For extra
precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to these P and N DC powerinput pins.
CUCVCW
Analogue signal output corresponding to
each phase current (5V line) Note 1)
U
P
V
P
W
P
U
N
V
N
W
N
B
r
CL FO1 FO2 FO3
Each phase input (PWM) Fault output
(5V line) Note 2)
(5V line) Note 3)
(Fig. 2)
MAXIMUM RATINGS
(Tj = 25°C)
INVERTER PART (Including Brake Part)
Supply voltage
V
CC(surge)
Supply voltage (surge)
V
P
or V
N
V
P(S)
or V
N(S)
±I
C
(±I
CP
)
I
C
(I
CP
)
I
F
(I
FP
)
Symbol
V
CC
Item
Condition
Applied between P2-N
Ratings
450
500
600
600
±8
(±16)
3 (6)
3 (6)
Unit
V
V
V
V
A
A
A
Applied between P2-N, Surge-value
Applied between P-U, V, W, Br or U, V, W,
Each output IGBT collector-emitter static voltage
Br-N
Each output IGBT collector-emitter
Applied between P-U, V, W, Br or U, V, W,
switching surge voltage
Br-N
Each output IGBT collector current
T
C
= 25°C
Brake IGBT collector current
Brake diode anode current
Note: “( )” means I
C
peak value
CONVERTER PART
Symbol
V
RRM
Ea
I
O
I
FSM
I
2
t
Item
Repetitive peak reverse voltage
Recommended AC input voltage
DC output current
Surge (non-repetitive) forward current
I
2
t
for fusing
Condition
Ratings
800
220
25
138
80
Unit
V
V
A
A
A
2
s
3φ rectifying circuit
1 cycle at 60Hz, peak value non-repetitive
Value for one cycle of surge current
CONTROL PART
Symbol
V
DH
, V
DB
V
CIN
V
FO
I
FO
V
CL
I
CL
I
CO
Supply voltage
Input signal voltage
Fault output supply voltage
Fault output current
Current-limit warning (CL) output voltage
CL output current
Analogue current signal output current
Item
Condition
Applied between V
DH
-GND, C
BU+
-C
BU–
,
C
BV+
-C
BV–
, C
BW+
-C
BW–
Applied between U
P
· V
P
· W
P
· U
N
· V
N
·
W
N
· B
r
-GND
Applied between F
O1
· F
O2
· F
O3
-GND
Sink current of F
O1
· F
O2
· F
O3
Applied between CL-GND
Sink current of CL
Sink current of CU · CV · CW
Ratings
20
–0.5 ~ 7.5
–0.5 ~ 7
15
–0.5 ~ 7
15
±1
Unit
V
V
V
mA
V
mA
mA
Jan. 2000
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11013
FLAT-BASE TYPE
INSULATED TYPE
TOTAL SYSTEM
Symbol
T
j
T
stg
T
C
V
iso
—
Item
Junction temperature
Storage temperature
Module case operating temperature
Isolation voltage
Mounting torque
Condition
(Note 2)
—
(Fig. 3)
60 Hz sinusoidal AC applied between all terminals and
the base plate for 1 minute.
Mounting screw: M3.5
Ratings
–20 ~ +125
–40 ~ +125
–20 ~ +100
2500
0.78 ~ 1.27
Unit
°C
°C
°C
Vrms
kg·cm
Note 2) The item defines the maximum junction temperature for the power elements (IGBT/Diode) of the ASIPM to ensure safe operation. How-
ever, these power elements can endure junction temperature as high as 150°C instantaneously . To make use of this additional tem-
perature allowance, a detailed study of the exact application conditions is required and, accordingly, necessary information is requested
to be provided before use.
CASE TEMPERATURE MEASUREMENT POINT (3mm from the base surface)
TC
(Fig. 3)
THERMAL RESISTANCE
Symbol
Rth(j-c)
Q
Rth(j-c)
F
Rth(j-c)
QB
Rth(j-c)
FB
Rth(j-c)
FR
Rth(c-f)
Contact Thermal Resistance
Junction to case Thermal
Resistance
Item
Inverter IGBT (1/6)
Inverter FWDi (1/6)
Brake IGBT
Brake FWDi
Converter Di (1/6)
Case to fin, thermal grease applied (1 Module)
Condition
Min.
—
—
—
—
—
—
Ratings
Typ.
—
—
—
—
—
—
Max.
4.1
6.1
6.1
6.1
4.8
0.053
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
ELECTRICAL CHARACTERISTICS
(Tj = 25°C, V
DH
= 15V, V
DB
= 15V unless otherwise noted)
Symbol
V
CE(sat)
V
EC
V
CE(sat)Br
V
FBr
I
RRM
V
FR
ton
tc(on)
toff
tc(off)
trr
FWD reverse recovery time
Short circuit endurance
(Output, Arm, and Load,
Short Circuit Modes)
Switching SOA
Item
Collector-emitter saturation voltage
FWDi forward voltage
Brake IGBT
Collector-emitter saturation voltage
Brake diode forward voltage
Condition
V
DH
= V
DB
= 15V, Input = ON, Tj = 25°C, I
C
= 8A
Tj = 25°C, I
C
= –8A, Input = OFF
V
DH
= 15V, Input = ON, Tj = 25°C, I
C
= 3A
Tj = 25°C, I
F
= 3A, Input = OFF
Min.
—
—
—
—
—
—
0.3
—
—
—
—
Ratings
Typ.
—
—
—
—
—
—
0.6
0.2
1.1
0.35
0.1
Max.
2.9
2.9
3.5
2.9
8
1.5
1.5
0.6
1.8
1.0
—
Unit
V
V
V
V
mA
V
µs
µs
µs
µs
µs
Converter diode reverse current V
R
= V
RRM
, Tj = 125°C
Tj = 25°C, I
F
= 5A
Converter diode voltage
1/2 Bridge inductive load, Input = ON
Switching times
V
CC
= 300V, Ic = 8A, Tj = 125°C
V
DH
= 15V, V
DB
= 15V
Note : ton, toff include delay time of the internal control
circuit
V
CC
≤
400V, Input = ON (one-shot)
Tj = 125°C start
13.5V
≤
V
DH
= V
DB
≤
16.5V
V
CC
≤
400V, Tj
≤
125°C,
Ic < I
OL
(CL) operation level, Input = ON
13.5V
≤
V
DH
= V
DB
≤
16.5V
• No destruction
• F
O
output by protection operation
• No destruction
• No protecting operation
• No F
O
output
Jan. 2000
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11013
FLAT-BASE TYPE
INSULATED TYPE
ELECTRICAL CHARACTERISTICS
(Tj = 25°C, V
DH
= 15V, V
DB
= 15V unless otherwise noted)
Symbol
I
DH
V
th(on)
V
th(off)
R
i
f
PWM
t
xx
t
dead
t
int
V
CO
Item
Circuit current
Input on threshold voltage
Input off threshold voltage
Input pull-up resistor
PWM input frequency
Allowable input on-pulse width
Allowable input signal dead time for
blocking arm shoot-through
Input inter-lock sensing
Condition
V
DH
= 15V, V
CIN
= 5V
Min.
—
0.8
2.5
—
2
1
2.2
—
1.87
0.77
2.97
—
—
4.0
—
–5
—
7.93
—
—
(Fig. 7) (Note 5)
13.2
100
—
11.05
11.55
18.00
T
C
= –20°C ~ +100°C
Tj
≤
125°C
16.50
10.0
10.5
—
—
—
Ratings
Typ.
—
1.4
3.0
150
—
—
—
65
2.27
1.17
3.37
15
—
—
1.1
—
3
10.80
—
1
24.0
110
90
12.00
12.50
19.20
17.50
11.0
11.5
10
—
1
Max.
150
2.0
4.0
—
20
500
—
100
2.57
1.47
3.67
—
0.7
—
—
5
—
13.90
1
—
34.3
120
—
12.75
13.25
20.15
18.65
12.0
12.5
—
1
—
Unit
mA
V
V
kΩ
kHz
µs
µs
ns
V
V
V
mV
V
V
V
%
µs
A
µA
mA
A
°C
°C
V
V
V
V
V
V
µs
µA
mA
Integrated between input terminal-V
DH
T
C
≤
100°C, Tj
≤
125°C
(Note 3)
V
DH
= 15V, T
C
= –20°C ~ +100°C
Relates to corresponding input
(Except brake part) T
C
= –20°C ~ +100°C
Relates to corresponding input (Except brake part)
Ic = 0A
Ic = I
OP
(200%)
Ic = –I
OP
(200%)
V
DH
= 15V
T
C
= –20°C ~ +100°C
(Fig. 4)
Analogue signal linearity with
V
C+
(200%)
output current
V
C–
(200%)
Offset change area vs temperature
|∆V
CO
|
V
C+
Analogue signal output voltage limit
V
C–
∆V
C
(200%) Analogue signal over all linear variation
r
CH
t
d(read)
±I
OL
I
CL(H)
I
CL(L)
SC
OT
OTr
UV
DH
UV
DHr
OV
DH
OV
DHr
UV
DB
UV
DBr
t
dV
I
FO(H)
I
FO(L)
Supply circuit under &
over voltage protection
Analogue signal data hold accuracy
Analogue signal reading time
Current limit warning (CL) operation level
Idle
Active
Short circuit over current trip level
Trip level
Over temperature protection
Reset level
Signal output current of
CL operation
Trip level
Reset level
Trip level
Reset level
Trip level
Reset level
Filter time
Idle
Active
V
DH
= 15V, T
C
= –20°C ~ +100°C
Ic > I
OP
(200%), V
DH
= 15V
(Fig. 4)
|V
CO
-V
C±
(200%)|
Correspond to max. 500µs data hold period
only, Ic = I
OP
(200%)
(Fig. 5)
After input signal trigger point
V
DH
=15V, T
C
= –20°C ~ +100°C
Open collector output
Tj = 25°C
V
DH
=15V
(Fig. 8)
(Note 4)
Fault output current
Open collector output
(Note 3) : (a) Allowable minimum input on-pulse width : This item applies to P-side circuit only.
(b) Allowable maximum input on-pulse width : This item applies to both P-side and N-side circuits excluding the brake circuit.
(Note4) : CL output : The "current limit warning (CL) operation circuit outputs warning signal whenever the arm current exceeds this limit. The
circuit is reset automatically by the next input signal and thus, it operates on a pulse-by-pulse scheme.
(Note5) : The short circuit protection works instantaneously when a high short circuit current flows through an internal IGBT rising up momen-
tarily. The protection function is, thus meant primarily to protect the ASIPM against short circuit distraction. Therefore, this function is
not recommended to be used for any system load current regulation or any over load control as this might, cause a failure due to
excessive temperature rise. Instead, the analogue current output feature or the over load warning feature (CL) should be appropri-
ately used for such current regulation or over load control operation. In other words, the PWM signals to the ASIPM should be shut
down, in principle, and not to be restarted before the junction temperature would recover to normal, as soon as a fault is feed back
from its F
O1
pin of the ASIPM indicating a short circuit situation.
RECOMMENDED CONDITIONS
Symbol
V
CC
V
DH
, V
DB
Item
Supply voltage
Control supply voltage
Condition
Applied across P2-N terminals
Applied between V
DH
-GND, C
BU+
-C
BU–
, C
BV+
-C
BV–
,
C
BW+
-C
BW–
Ratings
400 (max.)
15±1.5
±1
(max.)
0 ~ 0.3
4.8 ~ 5.0
Using application circuit
Using application circuit
2 ~ 20
2.2 (min.)
Unit
V
V
V/µs
V
V
kHz
µs
Jan. 2000
∆V
DH
,
∆V
DB
Supply voltage ripple
V
CIN(on)
Input on voltage
V
CIN(off)
Input off voltage
f
PWM
t
dead
PWM Input frequency
Arm shoot-through blocking time
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11013
FLAT-BASE TYPE
INSULATED TYPE
Fig. 4 OUTPUT CURRENT ANALOGUE SIG-
NALING LINEARITY
5
Fig. 5 OUTPUT CURRENT ANALOGUE SIGNALING
“DATA HOLD” DEFINITION
V
C
V
C
–
4
min
max
V
C
–
(200%)
V
DH
=15V
T
C
=
–
20
~
100˚C
500µs
0V
V
C0
3
V
C
(V)
V
CH
(5
µ
s)
V
CH
(505
µ
s)-V
CH
(5
µ
s)
V
CH
(5
µ
s)
V
CH
(505
µ
s)
2
V
C
+(200%)
r
CH
=
1
Analogue output signal
data hold range
V
C
+
0
–400 –300 –200 –100
0
100 200 300 400
Note ; Ringing happens around the point where the signal output
voltage changes state from “analogue” to “data hold” due
to test circuit arrangement and instrumentational trouble.
Therefore, the rate of change is measured at a 5
µs
delayed point.
Real load current peak value.(%)(I
c
=I
o
!
2)
(Fig. 4)
Fig. 6 INPUT INTERLOCK OPERATION TIMING CHART
Input signal V
CIN(p)
of each phase upper arm
Input signal V
CIN(n)
of each phase lower arm
0V
Gate signal V
o(p)
of each phase upper arm
(ASIPM internal)
Gate signal V
o(n)
of each phase upper arm
(ASIPM internal)
Error output F
O1
0V
0V
0V
0V
Note : Input interlock protection circuit ; It is operated when the input signals for any upper-arm / lower-arm pair of a phase are simulta-
neously in “LOW” level.
By this interlocking, both upper and lower IGBTs of this mal-triggered phase are cut off, and “F
O
” signal is outputted. After an “input
interlock” operation the circuit is latched. The “F
O
” is reset by the high-to-low going edge of either an upper-leg, or a lower-leg input,
whichever comes in later.
Fig. 7 TIMING CHART AND SHORT CIRCUIT PROTECTION OPERATION
Input signal V
CIN
of each phase
upper arm
Short circuit sensing signal V
S
0V
0V
S
C
delay time
Gate signal Vo of each phase
upper arm(ASIPM internal)
Error output F
O1
0V
0V
Note : Short circuit protection operation. The protection operates with “F
O
” flag and reset on a pulse-by-pulse scheme. The protection by
gate shutdown is given only to the IGBT that senses an overload (excluding the IGBT for the “Brake”).
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