Freescale Semiconductor
Advance Information
Document Number: MC33904_5
Rev. 3.0, 2/2010
System Basis Chip Gen2 with High
Speed CAN and LIN Interface
The 33904/5 is the second generation family of System Basis Chips
which combine several features and enhance present module designs.
The device works as an advanced power management unit for the
MCU and additional integrated circuits such as sensors, CAN
transceivers. It has a built-in enhanced high speed CAN interface
(ISO11898-2 and -5), with local and bus failure diagnostics, protection,
and fail safe operation mode. The SBC may include one or two LIN 2.1
interfaces with LIN output pin switches. It includes up to 4 wake-up
input pins than can also be configured as output drivers for flexibility.
This device implements multiple Low Power modes, with very low-
current consumption. In addition, the device is part of a family concept
where pin compatibility, among the various devices with and without
LIN interfaces, add versatility to module design.
The 33904/5 also implements an innovative and advanced fail-safe
state machine and concept solution.
33904
33904/5
33905
SBC CAN GEN2
EK SUFFIX (PB-FREE)
98ASA10556D
32-PIN SOIC EP
EK SUFFIX (PB-FREE)
98ASA10506D
54-PIN SOIC EP
Features
• Protected 5.0V or 3.3V regulators for MCU (part number selectable)
and additional ICs (SPI configurable) with optional external PNP
usage to increase current capability for MCU.
• Fully-protected embedded 5.0 V regulator for the CAN driver
• Extremely low quiescent current in low power modes
• Multiple under-voltage detections to address various MCU
specifications and system operation modes (i.e. cranking)
• Multiple wake-up sources in low power modes: CAN or LIN bus, I/O
transition, automatic timer, SPI message, and VDD over-current
detection.
• Voltage, current and temperature protection with enhanced
diagnostics that can be monitored by system via MUX output
• ISO11898-5 high speed CAN interface compatibility for baud rates
of 40 kb/s to 1.0 Mb/s. LIN 2.1 and J2602 LIN interface compatibility
• Pb-free packaging designated by suffix code EK
V
BAT
D1
ORDERING INFORMATION
Device
PCZ33905D3EK/R2
MCZ33905D5EK/R2
PCZ33905S3EK/R2
MCZ33905S5EK/R2
PCZ33904A3EK/R2
MCZ33904A5EK/R2
-40°C to 125°C
32 SOIC EP
Temperature
Range (T
A
)
Package
54 SOIC EP
33905D
(5.0 V/3.3 V)
* = Optional
Q2
Q1*
VBAUX VCAUX VSUP1 VAUX VE VB VDD
VSUP2
SAFE
DBG
GND
VSENSE
I/O-0
RST
INT
MOSI
SCLK
MISO
CS
MUX-OUT
5V-CAN
TXD
RXD
TXD-L1
RXD-L1
TXD-L2
RXD-L2
V
DD
SPI
A/D
MCU
I/O-1
CANH
SPLIT
CAN Bus
LIN Bus
LIN Bus
CANL
LIN-TERM 1
LIN-1
LIN-TERM 2
LIN-2
Figure 1. 33905D Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2010. All rights reserved.
V
BAT
D1
33905S
(5.0 V/3.3 V)
* = Optional
Q2
Q1*
VBAUX VCAUX VSUP1 VAUX VE VB VDD
VSUP2
SAFE
DBG
GND
VSENSE
I/O-0
RST
INT
MOSI
SCLK
MISO
CS
MUX-OUT
5V-CAN
TXD
RXD
TXD-L
RXD-L
V
DD
SPI
A/D
MCU
I/O-1
CANH
SPLIT
CAN Bus
V
BAT
CANL
LIN-T
LIN
I/O-3
LIN Bus
Figure 2. 33905S Simplified Application Diagram
V
BAT
D1
33904A
(5.0 V/3.3 V)
* = Optional
Q2
Q1*
VBAUX VCAUX VSUP1 VAUX VE VB VDD
VSUP2
SAFE
DBG
GND
VSENSE
I/O-0
RST
INT
MOSI
SCLK
MISO
CS
MUX-OUT
5V-CAN
TXD
RXD
V
DD
SPI
A/D
MCU
I/O-1
CANH
V
BAT
SPLIT
CAN Bus
CANL
I/O-2
I/O-3
Figure 3. 33904A Simplified Application Diagram
33904/5
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
DEVICE VARIATIONS
DEVICE VARIATIONS
Table 1. Device Variations
Freescale Part No.
PCZ33905D3EK/R2
MCZ33905D5EK/R2
Vdd output
voltage
3.3V
5V
1
2
CAN
interface
LIN
interface(s)
Wake up input / LIN master
termination
2 wake up + 2 LIN terms
or
3 wake up + 1 LIN terms
or
4 wake up + no LIN terms
PCZ33905S3EK/R2
MCZ33905S5EK/R2
PCZ33904A3EK/R2
MCZ33904A5EK/R2
3.3V
5V
3.3V
1
5V
no
4 wake up
1
1
3 wake up + 1 LIN terms
or
4 wake up + no LIN terms
SOIC 32pins
exposed pad
SOIC 32pins
exposed pad
SOIC 54 pins
exposed pad
Package
33904/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
TABLE OF CONTENTS
TABLE OF CONTENTS
Internal Block Diagram .............................................................................................................................. 5
Pin Connections ........................................................................................................................................ 8
Electrical Characteristics ......................................................................................................................... 12
Maximum Ratings ................................................................................................................................. 12
Static Electrical Characteristics ............................................................................................................ 14
Dynamic Electrical Characteristics ....................................................................................................... 21
Timing Diagrams .................................................................................................................................. 24
Functional Description ............................................................................................................................. 28
Introduction ........................................................................................................................................... 28
Functional Pin Description .................................................................................................................... 28
Functional Device Operation ................................................................................................................... 32
Mode and State Description ................................................................................................................. 32
Low Power Modes ................................................................................................................................ 33
State Diagram ....................................................................................................................................... 34
Mode Change ....................................................................................................................................... 35
Watchdog Operation ............................................................................................................................. 35
Functional Block Operation Versus Mode ............................................................................................ 37
Illustration of Device Mode Transitions. ................................................................................................ 37
Cyclic Sense Operation During LP Modes ........................................................................................... 39
Behavior at Power Up and Power Down .............................................................................................. 40
Fail Safe Operation ................................................................................................................................. 42
CAN Interface ....................................................................................................................................... 46
CAN Interface Description .................................................................................................................... 46
CAN Bus Fault Diagnostic .................................................................................................................... 50
LIN Block ................................................................................................................................................. 53
LIN Interface Description ...................................................................................................................... 53
LIN Operational Modes ......................................................................................................................... 53
Serial Peripheral Interface ....................................................................................................................... 55
High Level Overview ............................................................................................................................. 55
Detail Operation .................................................................................................................................... 56
Detail of Control Bits And Register Mapping ........................................................................................ 59
Flags ..................................................................................................................................................... 75
Typical Applications ................................................................................................................................ 80
Packaging ............................................................................................................................................... 84
33904/5
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VBAUX VCAUX VAUX
VSUP1
VE VB
VSUP2
5 V Auxiliary
Regulator
V
S2-INT
V
DD
Regulator
VDD
SAFE
RST
Fail-safe
DBG
GND
VSENSE
INT
MOSI
Power Management
Oscillator
State Machine
SPI
SCLK
MISO
CS
Analog Monitoring
Signals Condition & Analog MUX
MUX-OUT
I/O-0
I/O-1
CANH
SPLIT
CANL
V
S2-INT
V
S2-INT
Configurable
Input-Output
5 V-CAN
Regulator
5V-CAN
Enhanced High-speed CAN
Physical Interface
TXD
RXD
TXD-L1
LIN-TERM1
LIN-1
LIN-TERM2
LIN-2
V
S2-INT
LIN 2.1 Interface - #1
RXD-L1
TXD-L2
LIN 2.1 Interface - #2
RXD-L2
Figure 4. 33905D Internal Block Diagram
33904/5
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
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