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33904

Description
system basis chip gen2 with high speed can and lin interface
File Size1MB,91 Pages
ManufacturerFREESCALE (NXP)
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system basis chip gen2 with high speed can and lin interface

Freescale Semiconductor
Advance Information
Document Number: MC33904_5
Rev. 3.0, 2/2010
System Basis Chip Gen2 with High
Speed CAN and LIN Interface
The 33904/5 is the second generation family of System Basis Chips
which combine several features and enhance present module designs.
The device works as an advanced power management unit for the
MCU and additional integrated circuits such as sensors, CAN
transceivers. It has a built-in enhanced high speed CAN interface
(ISO11898-2 and -5), with local and bus failure diagnostics, protection,
and fail safe operation mode. The SBC may include one or two LIN 2.1
interfaces with LIN output pin switches. It includes up to 4 wake-up
input pins than can also be configured as output drivers for flexibility.
This device implements multiple Low Power modes, with very low-
current consumption. In addition, the device is part of a family concept
where pin compatibility, among the various devices with and without
LIN interfaces, add versatility to module design.
The 33904/5 also implements an innovative and advanced fail-safe
state machine and concept solution.
33904
33904/5
33905
SBC CAN GEN2
EK SUFFIX (PB-FREE)
98ASA10556D
32-PIN SOIC EP
EK SUFFIX (PB-FREE)
98ASA10506D
54-PIN SOIC EP
Features
• Protected 5.0V or 3.3V regulators for MCU (part number selectable)
and additional ICs (SPI configurable) with optional external PNP
usage to increase current capability for MCU.
• Fully-protected embedded 5.0 V regulator for the CAN driver
• Extremely low quiescent current in low power modes
• Multiple under-voltage detections to address various MCU
specifications and system operation modes (i.e. cranking)
• Multiple wake-up sources in low power modes: CAN or LIN bus, I/O
transition, automatic timer, SPI message, and VDD over-current
detection.
• Voltage, current and temperature protection with enhanced
diagnostics that can be monitored by system via MUX output
• ISO11898-5 high speed CAN interface compatibility for baud rates
of 40 kb/s to 1.0 Mb/s. LIN 2.1 and J2602 LIN interface compatibility
• Pb-free packaging designated by suffix code EK
V
BAT
D1
ORDERING INFORMATION
Device
PCZ33905D3EK/R2
MCZ33905D5EK/R2
PCZ33905S3EK/R2
MCZ33905S5EK/R2
PCZ33904A3EK/R2
MCZ33904A5EK/R2
-40°C to 125°C
32 SOIC EP
Temperature
Range (T
A
)
Package
54 SOIC EP
33905D
(5.0 V/3.3 V)
* = Optional
Q2
Q1*
VBAUX VCAUX VSUP1 VAUX VE VB VDD
VSUP2
SAFE
DBG
GND
VSENSE
I/O-0
RST
INT
MOSI
SCLK
MISO
CS
MUX-OUT
5V-CAN
TXD
RXD
TXD-L1
RXD-L1
TXD-L2
RXD-L2
V
DD
SPI
A/D
MCU
I/O-1
CANH
SPLIT
CAN Bus
LIN Bus
LIN Bus
CANL
LIN-TERM 1
LIN-1
LIN-TERM 2
LIN-2
Figure 1. 33905D Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2010. All rights reserved.

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