Freescale Semiconductor
Advance Information
Document Number: MC33784
Rev 3.0, 11/2009
DSI 2.02 Sensor Interface
The 33784 is a slave, Distributed System Interface Bus (DBUS),
version 2.02 compatible device, optimized as a sensor interface. The
device contains circuits to power sensors such as accelerometers,
and to digitize the analog level from the sensor. The device is
controlled by commands over the bus, and returns measured data
and other information over the bus.
Features
•
•
•
•
•
•
•
DSI version 2.02 compatible
2-channel, 10-bit analog-to-digital converter (ADC)
3 pins configurable as logic inputs or outputs
Provides regulated +5.0v output for sensor power from bus
On-board clock (no external elements required)
Includes bus switches on bus and bus return
Pb-free packaging designated by suffix code EF
33784
SENSOR INTERFACE
EF SUFFIX (PB-FREE)
98ASB42566B
16-LEAD SOICN
ORDERING INFORMATION
Device
MCZ33784EF/R2
Temperature
Range (T
A
)
- 40°C to 125°C
Package
16 SOICN
33781
BUS
33784
REGOUT
RTNIN
AGND
AN0
AN1
I/O0
I/O1
I/O2
BUSOUT
RTNOUT
BUSIN
H_CAP
IDDQ
TEST1
TOUT
TEST2
V
CC
BUSIN
RTNIN
33784
BUSOUT
RTNOUT
To other
33784
Slaves
XY
ACCELEROMETER
AGND
Figure 1. 33784 Simplified Application Diagram
(Daisy Chain Shown)
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2008 - 2009. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
H_CAP
Rectifier
BUSIN
High Side Bus Switch
0-35 V
Receiver
Data
Response
Current
0–11mA
8.0mA/μs
Received
Message
from MCU
Oscillator
10MHz
DataOut <2.0>
I/O Buffers
DataOut <0>
I/O0
I/O1
I/O2
TEST1
TEST2
MUX
DataOut <2>
SEL
10-Bit
ADC
POR
IDDQ
DataOut <1>
2.2μF or
4.7μF
Typical
BUSOUT
Frame
Bandgap
Reference
Bus Return
Logic
Command Decode
State Machine
Response Generation
Power
Management
5.0V Regulator
BG Reference
Bias Currents
TOUT
REGOUT
C
RO
= 2.2μF
AGND
AN0
AN1
RTNIN
Low Side Bus Switch
RTNOUT
Figure 2. 33784 Simplified Internal Block Diagram
33784
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
REGOUT
TEST2
I/O0
I/O1
I/O2
AN0
AGND
AN1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
H_CAP
BUSIN
BUSOUT
RTNIN
RTNOUT
TOUT
IDDQ
TEST1
Figure 3. 33784 Pin Connections
Table 1. 33784 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on
page 10.
Pin Number
1
2
3
4
5
6, 8
7
9
10
11
12
13
14
15
16
Pin Name
REGOUT
TEST2
I/O0
I/O1
I/O2
AN0,AN1
AGND
TEST1
IDDQ
TOUT
RTNOUT
RTNIN
BUSOUT
BUSIN
H_CAP
Pin
Function
Output
Test
Input/Output
Formal Name
Regulator
Output
Test2
Logic I/O
Definition
Pin provides a regulated 5.0V output. The power is derived from the bus.
This pin must be grounded in the application.
Pins can be used to provide a logic level output or a logic input.
Input
Ground
Reference
Test
Test
Test
Power
Power
Output
Input
Output
Analog Input
Analog Ground
Test1
IDDQ
Test Output
Bus Return
Bus Return
DBUS Output
DBUS Input
Holding
Capacitor
Inputs to the ADC.
Pin is the low reference level and power return for the analog-to-digital
converter (ADC). It is internally connected to RTNIN.
This pin must be grounded in the application.
Input pin for measuring device quiescent current. Must be left open in the
application.
This pin must be grounded in the application.
Switched RTNIN pin, attaches to the next RTNIN pin in the daisy chain.
Pin attaches to the low side of the differential bus, and provides the common
return for power and signalling. It is internally connected to AGND.
Switched BUSIN Pin, attaches to the next BUSIN pin in the daisy chain.
Pin attaches to the high side of the differential bus and responds to
initialization commands.
A capacitor attached to this pin is charged by the bus during bus idle and
supplies current to run the device and for external devices via the REGOUT
pin during non-idle periods.
33784
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to Analog Ground (AGND) unless otherwise noted. Exceeding these ratings may cause a
malfunction or permanent damage to the device.
Ratings
ELECTRICAL RATINGS
I /O0, I/O1, I/O2, AN0, AN1, TEST1, TEST2, TOUT Voltage
I /On, ANn, TESTn, TOUT Pin Current
BUSOUT Voltage, BUS SW = open
BUSIN Voltage, BUS SW = open
RTNOUT Voltage, BUS SW = open
H_CAP Voltage
BUSIN, BUSOUT, and H_CAP Current (Continuous)
BUSIN, RTNIN, reverse current (max 5 ms)
RTNIN, RTNOUT Current
IDDQ Voltage
V
REG
Range
ESD Voltage
(1)
Human Body Model (HBM)
Machine Model (MM)
Charge Device Model (CDM)
Corner pins
All other pins
THERMAL RATINGS
Storage Temperature
Operating Ambient Temperature
Operating Junction Temperature
THERMAL RESISTANCE AND PACKAGE DISSIPATION RATINGS
Resistance, Junction-to-Ambient (Single Layer (1s) PCB Board)
Resistance, Junction-to-Board (Multi-Layer (2s2P) PCB Board)
Peak Package Reflow Temperature During Reflow
(2)
,
(3)
R
θ
JA
R
θ
JB
T
PPRT
125
62
Note 3
°C/W
°C/W
°C
T
S
T
A
T
J
-55 to 150
-40 to 125
-40 to 150
°C
°C
°C
±750
±500
V
IO
I
IO
V
IN
V
IN
V
IN
V
IN
I
IN
I
REVLK
I
BUSRTN
V
IDDQ
V
RO
V
ESD
±2000
±200
-0.3 to V
REGOUT
+ 0.3
5.0
-14 to 40
-0.3 to 40
-14 to 25
-0.3 to 40
400
400
400
2.75
0.3 - 7.0
V
mA
V
V
V
V
mA
mA
mA
V
V
V
Symbol
Value
Unit
Notes
1. ESD1 testing is performed in accordance with the Human Body Model (HBM) (C
ZAP
= 100pF, R
ZAP
= 1500Ω), ESD2 testing is
performed in accordance with the Machine Model (MM) (C
ZAP
= 200pF, R
ZAP
= 0Ω); and Charge Body Model (CBM)
2.
3.
Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
33784
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions -0.3V
≤
V
BUSIN
≤
30V, 6.0V
≤
V
H_CAP
≤
30V, - 40°C
≤
T
A
≤
125°C,
RTNIN=AGND = 0V, unless otherwise noted. Typical values noted reflect the approximate parameter means at T
A
= 25°C under
nominal conditions, unless otherwise noted.
Characteristic
Internal Quiescent Current Drain
V
H_CAP
= 25V, I /O = Input
BUSIN to H_CAP Rectifier Voltage Drop
I
HCAP
= 15mA
I
HCAP
= 100mA
H_CAP Diode Efficiency
(4)
I
HCAP
= 400mA, BUSIN = 25V
BUSIN Bias Current
V
BUSIN
= 8.0V, V
H_CAP
= 9.0V
V
BUSIN
= 4.5V, V
H_CAP
= 9.0V when device is not signalling
Rectifier Leakage Current
V
BUSIN
= 0V, V
H_CAP
= 25V
REGOUT
5.8V
<
V
H_CAP
≤
25V, 0
≤
I
RO
≤
14mA
REGOUT Line Regulation
I
RO
= 14mA, 6.0V
≤
V
H CAP
≤
25V
I
RO
is the total internal and external load current
REGOUT Load Regulation
0
≤
I
RO
≤
14mA, 6.0V
≤
V
H CAP
≤
25V,
REGOUT Transient Line Regulation
(5)
I
RO
= 14mA, 0 V
≤
V
BUSIN
≤
30 V, 8V/us @ BUSIN, or, 5V/us @
HCAP
C
RO
= 2.2 uF, C
RO
ESR = 0.063-2.2Ω @ 20kHz,
0.004-0.072Ω @ 200kHz
REGOUT Transient Load Regulation
(5)
0
≤
I
RO
≤
14mA, 6.0V
≤
V
H CAP
≤
25V, 2mA/us @ I
RO,
C
RO
= 2.2uF, C
RO
ESR = 0.063-2.2Ω @ 20kHz,
0.004-0.072Ω @ 200kHz
REGOUT Current Limit, V
REGOUT
= 0V
Hi-side Bus Switch Resistance
0
≤
V
BUSIN
≤ 30
V, I
SWH
= 160mA (Bus Switch Active)
Low-side Bus Switch Resistance
I
SWL
= 160mA (Bus Switch Active)
Notes
4. E
FF
= 400mA/I
BUSIN
- I
Q
5.
Assured by design.
R
SWL
–
3.0
6.0
I
LMT
R
SWH
–
3.0
6.0
Ω
25
35
45
mA
Ω
–
–
(50)
mV
–
–
(25)
mV
VR
LD
–
–
15
mV
VR
LINE
–
–
20
mV
V
RO
4.9
5.0
5.1
V
I
RLKG
I
BIAS
-100
-100
-20
–
–
100
100
20
μA
99
–
–
μA
V
RECT
–
–
0.75
0.9
1.00
1.4
%
Symbol
I
Q
–
–
4.0
V
Min
Typ
Max
Unit
mA
33784
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
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