74ABT240 Octal Buffer/Line Driver with 3-STATE Outputs
March 1994
Revised March 2005
74ABT240
Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The ABT240 is an inverting octal buffer and line driver
designed to be employed as a memory address driver,
clock driver and bus oriented transmitter or receiver which
provides improved PC board density.
Features
s
Output sink capability of 64 mA, source capability of
32 mA
s
Guaranteed latchup protection
s
High impedance glitch free bus loading during entire
power up and power down cycle
s
Nondestructive hot insertion capability
Ordering Code:
Order Number
74ABT240CSC
74ABT240CSJ
74ABT240CMSA
74ABT240CMTC
Package Number
M20B
M20D
MSA20
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Pin Descriptions
Pin Names
OE
1
, OE
2
Description
3-STATE Output
Enable Inputs
I
0
–I
7
O
0
–O
7
Inputs
Outputs
Truth Tables
Inputs
OE
1
L
L
H
Inputs
OE
2
L
L
H
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
Outputs
I
n
L
H
X
(Pins 12, 14, 16, 18)
H
L
Z
Outputs
I
n
L
H
X
(Pins 3, 5, 7, 9)
H
L
Z
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DS011664
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74ABT240
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Any Output
in the Disabled or
Power-Off State
in the HIGH State
Current Applied to Output
in LOW State (Max)
DC Latchup Source Current
(Across Comm Operating Range)
Over Voltage Latchup (I/O)
twice the rated I
OL
(mA)
65
q
C to
150
q
C
55
q
C to
150
q
C
0.5V to
7.0V
0.5V to
7.0V
30 mA to
5.0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
Minimum Input Edge Rate (
'
V/
'
t)
Data Input
Enable Input
50 mV/ns
20 mV/ns
40
q
C to
85
q
C
4.5V to
5.5V
0.5V to 5.5V
0.5V to V
CC
150 mA
10V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
IL
V
ID
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Current
Input HIGH Current Breakdown Test
Input LOW Current
Input Leakage Test
4.75
2.5
2.0
0.55
1
1
7
Min
2.0
0.8
Typ
Max
Units
V
V
V
V
V
V
Min
Min
Min
Min
Max
Max
Max
0.0
V
CC
Conditions
Recognized HIGH Signal
Recognized LOW Signal
I
IN
I
OH
I
OH
I
OL
V
IN
V
IN
V
IN
V
IN
V
IN
I
ID
1.2
18 mA
3 mA
32 mA
64 mA
2.7V (Note 3)
V
CC
7.0V
0.5V (Note 3)
0.0V
1.9
P
A
P
A
P
A
P
A
V
1
1
All Other Pins Grounded
I
OZH
I
OZL
I
OS
I
CEX
I
ZZ
I
CCH
I
CCL
I
CCZ
I
CCT
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
Additional I
CC
/Input
Outputs Enabled
Outputs 3-STATE
Outputs 3-STATE
I
CCD
Dynamic I
CC
(Note 3)
Note 3:
Guaranteed, but not tested.
Note 4:
For 8 bits toggling, I
CCD
0.8 mA/MHz.
10
P
A
P
A
mA
0
5.5V V
OUT
0
5.5V V
OUT
Max
V
OUT
Max
0.0
Max
Max
Max
V
OUT
V
OUT
2.7V; OE
n
0.5V; OE
n
0.0V
V
CC
2.0V
2.0V
10
100
275
50
100
50
30
50
1.5
1.5
50
P
A
P
A
P
A
mA
5.5V; All Others GND
All Outputs HIGH
All Outputs LOW
OE
n
V
I
V
CC
;
V
CC
2.1V
V
CC
2.1V
V
CC
2.1V
P
A
mA
mA
All Others at V
CC
or Ground
Enable Input V
I
Data Input V
I
Outputs Open
Max
OE
n
GND, (Note 4)
One Bit Toggling, 50% Duty Cycle
P
A
mA/
Max
All Others at V
CC
or Ground
No Load
0.1
MHz
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2
74ABT240
AC Electrical Characteristics
T
A
V
CC
Symbol
Parameter
Min
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation Delay
Data to Outputs
Output Enable
Time
Output Disable
Time
1.0
1.6
1.1
1.1
1.8
1.6
C
L
25
q
C
5V
50 pF
Typ
Max
4.8
4.8
6.2
6.2
6.4
5.8
T
A
55
q
C to
125
q
C
4.5V–5.5V
50 pF
Max
5.5
5.5
7.5
7.7
7.5
7.2
C
L
Min
0.8
1.0
0.8
0.8
1.0
1.0
T
A
40
q
C to
85
q
C
4.5V–5.5V
50 pF
Max
4.8
4.8
6.2
6.2
6.4
5.8
ns
ns
ns
Units
C
L
V
CC
V
CC
Min
1.0
1.6
1.1
1.1
1.8
1.6
Capacitance
Symbol
C
IN
C
OUT
(Note 5)
Parameter
Input Capacitance
Output Capacitance
Typ
5.0
9.0
1 MHz, per MIL-STD-883, Method 3012.
Units
pF
pF
V
CC
V
CC
0V
5.0V
Conditions
T
A
25
q
C
Note 5:
C
OUT
is measured at frequency f
3
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74ABT240
AC Loading
*Includes jig and probe capacitance
Standard AC Test Load
Amplitude
3.0V
Test Input Signal Requirements
Test Input Signal Levels
Rep. Rate
1 MHz
t
W
500 ns
t
r
2.5 ns
t
f
2.5 ns
AC Waveforms
Propagation Delay,
Pulse Width Waveforms
Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
3-STATE Output HIGH
and LOW Enable and Disable Times
Setup Time, Hold Time
and Recovery Time Waveforms
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4
74ABT240
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
5
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