INTEGRATED CIRCUITS
MIPS
PR31500
Poseidon embedded processor
Preliminary specification
Version 0.1
1996 Sep 24
Philips
Semiconductors
Philips Semiconductors
Preliminary specification
Poseidon embedded processor
Version 0.1
GENERAL DESCRIPTION
PR31500 Processor is a single-chip, low-cost, integrated embedded
processor consisting of MIPS R3000 core and system support logic
to interface with various types of devices.
PR31500 consists of a MIPS R3000 RISC CPU with 4 KBytes of
instruction cache memory and 1 KByte of data cache memory, plus
integrated functions for interfacing to numerous system components
and external I/O modules. The R3000 RISC CPU is also augmented
with a multiply/accumulate module to allow integrated DSP
functions, such as a software modem for high-performance standard
data and fax protocols.
The PR31500 processor can support both Little and Big Endian
operating systems. In addition the PR31500 provides a memory
management unit with an on-chip Translation Look aside Buffer
(TLB) for very fast virtual to physical address translation.
PR31500 also contains multiple DMA channels and a
high-performance and flexible Bus Interface Unit (BIU) for providing
an efficient means for transferring data between external system
memory, cache memory, the CPU core, and external I/O modules.
The types of external memory devices supported include dynamic
random access memory (DRAM), synchronous dynamic random
access memory (SDRAM), static random access memory (SRAM),
Flash memory, read-only memory (ROM), and expansion cards
(e.g., PCMCIA). PR31500 also contains a System Interface Module
(SIM) containing integrated functions for interfacing to numerous
external I/O modules such as liquid crystal displays (LCDs), the
UCB1100 (which handles most of the analog functions of the
system, including sound and telecom codecs and touchscreen
ADC), ISDN/high-speed serial, infrared, wireless peripherals, etc.
Lastly, PR31500 contains support for implementation of power
management, whereby various PR31500 internal modules and
external subsystems can be individually (under software control)
powered up and down.
Figure 1 shows an External Block Diagram of PR31500.
MIPS
PR31500
FEATURES
•
32-bit R3000 RISC static CMOS CPU
•
4 KByte instruction cache
•
1 KByte data cache
•
Multiply/accumulator Instruction
•
R3000A memory management unit with on-chip TLB
•
Supports Big/Little Endian operating systems
•
On-chip peripherals with individual power-down
–
Multi-channel DMA controller
–
Bus interface unit
–
Memory controller for ROM, Flash, RAM, DRAM, SDRAM,
SRAM, and PCMCIA
–
Power management module
–
Video module
–
Real-time clock 32.760KHz reference
–
High-speed serial interface
–
Infrared module
–
Dual-UART
–
SPI bus
•
3.3V supply voltage
•
208-pin LQFP (Low profile quad flat pack)
•
40MHz operation frequency
ORDERING INFORMATION
PART NUMBER
PR31500ABC
TEMPERATURE RANGE (°C) AND PACKAGE
0 to +70, 208-pin Low Profile Quad Flat Pack
FREQUENCY
(MHz)
40
DRAWING NUMBER
LQFP208
1996 Sep 24
2
Philips Semiconductors
Preliminary specification
Poseidon embedded processor
MIPS
PR31500
ICache
DATA
4KByte
ADDR
TAG
Bus Interface Unit (BIU) Module
Data
Data
to
Memory
Addr
(S)DRAM/PCMCIA/ROM
R3000 RISC
CPU Core
MMU
Addr
MAC
Control
CPU
Module
DCache
1KByte
to UCB1100
to LCD
to general
purpose I/O
32 KHz
SYSCLK
1996 Sep 24
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System Interface Unit (SIU) Module
Arbitration/DMA/AddrDecode
Data
Addr
SIB Module
CHI Module
Video Module
IR Module
UART Module
(dual UART)
IO Module
SPI Module
Timer Module
(+ RTC)
Power Module
Clock Module
Interrupt Module
System Interface Module (SIM)
Figure 1. PR31500 Block Diagram
3
to high
speed serial
to IR
to UART
to Power
Supply
SN00162
Philips Semiconductors
Preliminary specification
Poseidon embedded processor
MIPS
PR31500
•
high-speed multiplier/accumulator
–
on-chip hardware multiplier
–
supports 16x16 or 32x32 multiplier operations, with 64-bit
accumulator
–
existing multiply instructions are enhanced and new multiply
and add instructions are added to R3000 instruction set to
improve the performance of DSP applications
OVERVIEW
Each of the on-chip peripherals consist of:
BIU Module
•
System memory and PR31500 Bus Interface Unit (BIU)
–
supports up to 2 banks of physical memory
–
supports self-refreshing DRAM and SDRAM
–
programmable parameters for each bank of DRAM or SDRAM
(row/column address configuration, refresh, burst modes, etc.)
•
CPU interface
–
handles data bus, address bus, and control interface between
CPU core and rest of PR31500 logic
•
programmable chip select memory access
–
4 programmable (size, wait states, burst mode control) memory
device and general purpose chip selects
available for system ROM, SRAM, Flash
available for external port expansion registers
Clock Module
•
PR31500 supports system-wide single crystal configuration,
besides the 32 KHz RTC XTAL (reduces cost, power, and board
space)
•
supports up to 2 identical full PCMCIA ports
–
PR31500 and UCB1100 provide the control signals and accepts
the status signals which conform to the PCMCIA version 2.01
standard
–
appropriate connector keying and level-shifting buffers required
for 3.3V versus 5V PCMCIA interface implementations
•
common crystal rate divided to generate clock for CPU, video,
sound, telecom, UARTs, etc.
•
external system crystal rate is vendor-dependent
•
independent enabling or disabling of individual clocks under
software control, for power management
SIU Module
(SIU)
•
multi-channel 32-bit DMA controller and System Interface Unit
•
independent DMA channels for video, SIB to/from UCB1100
audio/telecom codecs, high-speed serial port, IR UART, and
general purpose UART
CHI Module
•
high-speed serial Concentration Highway Interface (CHI) contains
logic for interfacing to external full-duplex serial
time-division-multiplexed (TDM) communication peripherals
•
supports ISDN line interface chips and other PCM/TDM serial
devices
•
address decoding for submodules within System Interface Module
(SIM)
•
CHI interface is programmable (number of channels, frame rate,
bit rate, etc.) to provide support for a variety of formats
CPU Module
•
R3000 RISC central processing unit core
–
full 32-bit operation (registers, instructions, addresses)
–
32 general purpose 32-bit registers; 32-bit program counter
–
MIPS RISC Instruction Set Architecture (ISA) supported
•
supports data rates up to 4.096 Mbps
•
independent DMA support for CHI receive and transmit
Interrupt Module
•
contains logic for individually enabling, reading, and clearing all
PR31500 interrupt sources
•
on-chip cache
–
4 KByte direct-mapped instruction cache (I-cache)
physical address tag and valid bit per cache line
programmable burst size
instruction streaming mode supported
–
1 KByte data cache (D-cache)
physical address tag and valid bit per cache line
programmable burst size
write-through
–
cache address snoop mode supported for DMA
–
4-level deep write buffer
•
interrupts generated from internal PR31500 modules or from edge
transitions on external signal pins
IO Module
•
contains support for reading and writing the 7 bi-directional
general purpose IO pins and the 32 bi-directional multi-function IO
pins
•
each IO port can generate a separate positive and negative edge
interrupt
•
independently configurable IO ports allow PR31500 to support a
flexible and wide range of system applications and configurations
•
Memory Management Unit
–
MIPS R3000A MMU contains on-chip TLB with:
32×64 bit wide entries
fully associative
2 entry micro TLB for very fast instruction address translation
Instruction address translation accesses full TLB after micro
TLB miss
Data address translation accesses full TLB
1996 Sep 24
4
Philips Semiconductors
Preliminary specification
Poseidon embedded processor
MIPS
PR31500
•
PR31500 supplies dedicated chip select and interrupt for an SPI
interface serial power supply
IR Module
•
IR consumer mode
–
allows control of consumer electronic devices such as stereos,
TVs, VCRs, etc.
–
programmable pulse parameters
–
external analog LED circuitry
•
8-bit or 16-bit data word lengths for the SPI interface
•
programmable SPI baud rate
Timer Module
•
IRDA communication mode
–
allows communication with other IRDA devices such as FAX
machines, copiers, printers, etc.
–
supported by UART module within PR31500
–
external analog receiver preamp and LED circuitry
–
data rate = up to 115 Kbps at 1 meter
•
Real Time Clock (RTC) and Timer
•
40-bit counter (30.517
µsec
granularity);
maximum uninterrupted time = 388.36 days
•
IR FSK communication mode
–
supported by UART module within PR31500
–
external analog IR chip(s) perform frequency modulation to
generate the desired IR communication mode protocol
–
data rate = up to 36000 bps at 3 meters
•
40-bit alarm register (30.517
µsec
granularity)
•
16-bit periodic timer (0.868
µsec
granularity);
maximum timeout = 56.8 msec
•
interrupts on alarm, timer, and prior to RTC roll-over
UART Module
•
carrier detect state machine
–
periodically enables IR receiver to check if a valid carrier is
present
•
2 independent full-duplex UARTs
•
programmable baud rate generator
•
UART-A port used for serial control interface to external IR
module
Power Module
•
power-down modes for individual internal peripheral modules
•
serial (SPI port) power supply control interface supported
•
power management state machine has 4 states: RUNNING,
DOZING, SLEEP, and COMA
•
UART-B port used for general purpose serial control interface
•
UART-A and UART-B DMA support for receive and transmit
Video Module
Serial Interconnect Bus (SIB) Module
•
PR31500 contains holding and shift registers to support the serial
interface to the UCB1100 and/or other optional codec devices
•
interface compatible with slave mode 3 of Crystal CS4216 codec
•
synchronous, frame-based protocol
•
PR31500 always master source of clock and frame frequency and
phase; programmable clock frequency
•
bit-mapped graphics
•
supports monochrome, grey scale, or color modes
•
time-based dithering algorithm for grey scale and color modes
•
supports multiple screen sizes
•
supports split and non-split displays
•
variable size and relocatable video buffer
•
DMA support for fetching image data from video buffer
Little/Big Endian Configuration
The PR31500 can be configures as a Big Endian or as a Little
Endian processor based on the /LB endian pin at power-up.
The byte ordering is as follows:
LITTLE ENDIAN
D[31:24]
D[23:16]
D[15:8]
D[7:0]
/CAS3
/CAS2
/CAS1
/CAS0
BIG ENDIAN
D[7:0]
D[15:8]
D[23:16]
D[31:24]
/CAS0
/CAS1
/CAS2
/CAS3
•
each SIB frame consists of 128 clock cycles, further divided into 2
subframes or words of 64 bits each (supports up to 2 devices
simultaneously)
•
independent DMA support for audio receive and transmit, telecom
receive and transmit
•
supports 8-bit or 16-bit mono telecom formats
•
supports 8-bit or 16-bit mono or stereo audio formats
•
independently programmable audio and telecom sample rates
•
CPU read/write registers for subframe control and status
System Peripheral Interface (SPI) Module
•
provides interface to SPI peripherals and devices
•
full-duplex, synchronous serial data transfers (data in, data out,
and clock signals)
1996 Sep 24
5
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