K7Q163682A
K7Q161882A
Document Title
512Kx36-bit, 1Mx18-bit QDR
TM
SRAM
512Kx36 & 1Mx18 QDR
TM
b2 SRAM
Revision History
Rev. No.
0.0
0.1
History
1. Initial document.
1. Icc, Isb addition
2. 1.8V Vddq addition
3. Speed bin change
1. Changed Pin configuration at x36 organization.
- 9F ; from Q14 to D14 .
- 10F ; from D14 to Q14 .
2. Reserved pin for high density name change from NC to Vss/SA
1. Final SPEC release
2. Modify thermal resistance
Draft Date
May, 22 2001
Remark
Advance
Sep,03 2001
Advance
0.2
Nov. 20. 2001
Preliminary
1.0
July, 03. 2002
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
July 2002
Rev 1.0
K7Q163682A
K7Q161882A
512Kx36-bit, 1Mx18-bit QDR
TM
SRAM
FEATURES
• 1.8V+0.1V/-0.1V Power Supply.
• I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O,
1.8V+0.1V/-0.1V for 1.8V I/O.
• Separate independent read and write data ports
with concurrent read and write operation
• HSTL I/O
• Full data coherency, providing most current data .
• Synchronous pipeline read with self timed early write.
• Registered address, control and data input/output.
• DDR(Double Data Rate) Interface on read and write ports.
• Fixed 2-bit burst for both read and write operation.
• Clock-stop supports to reduce current.
• Two Input clocks(K and K) for accurate DDR timing at clock
rising edges only.
• Two Input clocks for output data(C and C) to minimize clock-
skew and flight-time mismatches.
• Single address bus.
• Byte writable function.
• Sepatate read/write control pin(R and W)
• Simple depth expansion with no data contention.
• Programmable output impenance.
• JTAG 1149.1 compatible test access port.
• 165FBGA(11x15 ball aray FBGA) with body size of 13x15mm
512Kx36 & 1Mx18 QDR
TM
b2 SRAM
Organization
Part
Number
K7Q163682A-FC15
Cycle
Time
6.7
7.5
10.0
6.7
7.5
10.0
Access
Unit
Time
2.7
3.0
3.0
2.7
3.0
3.0
ns
ns
ns
ns
ns
ns
X36
K7Q163682A-FC13
K7Q163682A-FC10
K7Q161882A-FC15
X18
K7Q161882A-FC13
K7Q161882A-FC10
FUNCTIONAL BLOCK DIAGRAM
36 (or 18)
D(Data in)
DATA
REG
36 (or 18)
36 (or 18)
WRITE DRIVER
18 (or 19)
ADDRESS
WRITE/READ DECODE
ADD
REG
18 (or 19)
OUTPUT SELECT
OUTPUT DRIVER
R
W
BW
X
4(or 2)
CTRL
LOGIC
512Kx36
1Mx18
MEMORY
ARRAY
SENSE AMPS
72
(or 36)
OUTPUT REG
72
(or 36)
36 (or 18)
Q(Data Out)
K
K
C
C
CLK
GEN
SELECT OUTPUT CONTROL
Notes:
1. Numbers in ( ) are for x18 device.
QDR SRAM and Quad Data Rate comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC and Samsung technology.
-2-
July 2002
Rev 1.0
K7Q163682A
K7Q161882A
512Kx36 & 1Mx18 QDR
TM
b2 SRAM
PIN CONFIGURATIONS
(TOP VIEW)
K7Q161882A(1Mx18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
/SA*
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
3
NC/SA*
D9
D10
Q10
Q11
D12
Q13
V
DDQ
D14
Q14
D15
D16
Q16
Q17
SA
4
W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
BW
1
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
7
NC
BW
0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
R
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
V
SS
/SA*
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
11
NC
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Notes:
1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 3A for 32Mb, 10A for 64Mb and 2A for 128Mb.
2. BW
0
controls write to D0:D8 and BW
1
controls write to D9:D17.
PIN NAME
SYMBOL
K, K
C, C
SA
D
0-17
Q
0-17
W
R
BW
0
, BW
1
V
REF
ZQ
V
DD
V
DDQ
V
SS
TMS
TDI
TCK
TDO
NC
PIN NUMBERS
6B, 6A
6P, 6R
9A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
10P,11N,11M,10K,11J,11G,10E,11D,11C,3B,3C,2D,
3F,2G,3J,3L,3M,2N
11P,10M,11L,11K,10J,11F,11E,10C,11B,2B,3D,3E,
2F,3G,3K,2L,3N,3P
4A
8A
7B, 5A
2H,10H
11H
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
2A,10A,4C,8C,4D-8D,5E-7E,
6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
10R
11R
2R
1R
1A,3A,7A,11A,1B,5B,9B,10B,1C,2C,9C,1D,9D,10D,
1E,2E,9E,1F,9F,10F,1G,9G,10G,1H,1J,2J,9J,1K,
2K,9J,1L,9L,10L,1M,2M,9M,1N,9N,10N,1P,2P,9P
DESCRIPTION
Input Clock
Input Clocks for Output data
Address Inputs
Data Inputs
1
NOTE
Data Outputs
Write Control
Read Control
Byte Write Control
Input Reference Voltage
Output Driver Impedance Control Input
Power Supply ( 1.8 V )
Output Power Supply (1.5V or 1.8V)
Ground
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Clock
JTAG Test Data Output
No Connect
3
2
Notes:
1. C, C, K or K cannot be set to V
REF
voltage.
2. When ZQ pin is directly connected to V
DD
output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
-3-
July 2002
Rev 1.0
K7Q163682A
K7Q161882A
512Kx36 & 1Mx18 QDR
TM
b2 SRAM
PIN CONFIGURATIONS
(TOP VIEW)
K7Q163682A(512Kx36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
Q27
D27
D28
Q29
Q30
D30
NC
D31
Q32
Q33
D33
D34
Q35
TDO
2
V
SS
/SA*
Q18
Q28
D20
D29
Q21
D22
V
REF
Q31
D32
Q24
Q34
D26
D35
TCK
3
NC/SA*
D18
D19
Q19
Q20
D21
Q22
V
DDQ
D23
Q23
D24
D25
Q25
Q26
SA
4
W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
BW
2
BW
3
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
7
BW
1
BW
0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
R
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
NC/SA*
D17
D16
Q16
Q15
D14
Q13
V
DDQ
D12
Q12
D11
D10
Q10
Q9
SA
10
V
SS
/SA*
Q17
Q7
D15
D6
Q14
D13
V
REF
Q4
D3
Q11
Q1
D9
D0
TMS
11
NC
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Notes :
1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 9A for 32Mb, 3A for 64Mb, 10A for 128Mb and 2A for 256Mb.
2. BW
0
controls write to D0:D8, BW
1
controls write to D9:D17, BW
2
controls write to D18:D26 and BW
3
controls write to D27:D35.
PIN NAME
SYMBOL
K, K
C, C
SA
D0-35
PIN NUMBERS
6B, 6A
6P, 6R
4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
10P,11N,11M,10K,11J,11G,10E,11D,11C,10N,9M,9L
9J,10G,9F,10D,9C,9B,3B,3C,2D,3F,2G,3J,3L,3M,2N
1C,1D,2E,1G,1J,2K,1M,1N,2P
11P,10M,11L,11K,10J,11F,11E,10C,11B,9P,9N,10L
9K,9G,10F,9E,9D,10B,2B,3D,3E,2F,3G,3K,2L,3N
3P,1B,2C,1E,1F,2J,1K,1L,2M,1P
4A
8A
7B,7A,5A,5B
2H,10H
11H
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
2A,10A,4C,8C,4D-8D,5E-7E,
6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
10R
11R
2R
1R
1A,3A,9A,11A,1H
DESCRIPTION
Input Clock
Input Clocks for Output data
Address Inputs
Data Inputs
1
NOTES
Q0-35
W
R
BW
0
, BW
1,
BW
2
, BW
3
V
REF
ZQ
V
DD
V
DDQ
V
SS
TMS
TDI
TCK
TDO
NC
Data Outputs
Write Control Pin
Read Control Pin
Byte Write Control Pin
Input Reference Voltage
Output Driver Impedance Control Input
Power Supply ( 1.8 V )
Output Power Supply (1.5V or 1.8V)
Ground
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Clock
JTAG Test Data Output
No Connect
3
2
Notes:
1. C, C, K or K cannot be set to V
REF
voltage.
2. When ZQ pin is directly connected to V
DD
output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
-4-
July 2002
Rev 1.0
K7Q163682A
K7Q161882A
GENERAL DESCRIPTION
512Kx36 & 1Mx18 QDR
TM
b2 SRAM
The K7Q163682A and K7Q161882A are 18,874,368-bits QDR(Quad Data Rate) Synchronous Pipelined Burst SRAMs.
They are organized as 524,288 words by 36bits for K7Q163682A and 1,048,576 words by 18 bits for K7Q161882A.
The QDR operation is possible by supporting DDR read and write operations through separate data output and input ports
with the same cycle. Memory bandwidth is maxmized as data can be transfered into sram
on every rising edge of K and K, and transfered out of sram on every rising edge of C and C.
And totally independent read and write ports eliminate the need for high speed bus turn around.
Address, data inputs, and all control signals are synchronized to the input clock ( K or K ).
Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high,
the data outputs are synchronized to the input clocks ( K and K ).
Read address is registered on rising edges of the input K clocks, and write address is
registered on rising edges of the input K clocks.
Common address bus is used to access address both for read and write operations.
The internal burst counter is fiexd to 2-bit sequential for both read and write operations.
Synchronous pipeline read and early write enable high speed operations.
Simple depth expansion is accomplished by using R and W for port selection.
Byte write operation is supported with BW
0
and BW
1
( BW
2
and BW
3 )
pins.
IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoriing package pads attachment status with system.
The K7Q163682A and K7Q161882A are implemented with SAMSUNG's high performance 6T CMOS technology and is available
in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.
Read Operations
Read cycles are initiated by activating R at the rising edge of the positive input clock K.
Address is presented and stored in the read address register synchronized with K clock.
For 2-bit burst DDR operation, it will access two 36-bit or 18-bit data words with each read command.
The first pipelined data is transfered out of the device triggered by C clock following next K clock rising edge.
Next burst data is triggered by the rising edge of following C clock rising edge.
Continuous read operations are initiated with K clock rising edge.
And pipelined data are transferred out of device on every rising edge of both C and C clocks.
In case C and C tied to high, output data are triggered by K and K instead of C and C.
When the R is disabled after a read operation, the K7Q163682A and K7Q161882A will first complete burst read operation
before entering into deselect mode at the next K clock rising edge.
Then output drivers disabled automatically to high impedance state.
-5-
July 2002
Rev 1.0
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