K7Q161882 datasheet, PDF - EEWORLD Datasheet

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K7Q161882: Description512Kx36 & 1Mx18 QDR b2 SRAM; File Size357KB，17 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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512Kx36 & 1Mx18 QDR b2 SRAM

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K7Q163682A

K7Q161882A

Document Title

512Kx36-bit, 1Mx18-bit QDR

SRAM

512Kx36 & 1Mx18 QDR

b2 SRAM

Revision History

Rev. No.

0.0

0.1

History

1. Initial document.

1. Icc, Isb addition

2. 1.8V Vddq addition

3. Speed bin change

1. Changed Pin configuration at x36 organization.

- 9F ; from Q14 to D14 .

- 10F ; from D14 to Q14 .

2. Reserved pin for high density name change from NC to Vss/SA

1. Final SPEC release

2. Modify thermal resistance

Draft Date

May, 22 2001

Remark

Advance

Sep,03 2001

Advance

0.2

Nov. 20. 2001

Preliminary

1.0

July, 03. 2002

Final

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-

tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

-1-

July 2002

Rev 1.0

K7Q163682A

K7Q161882A

GENERAL DESCRIPTION

512Kx36 & 1Mx18 QDR

b2 SRAM

The K7Q163682A and K7Q161882A are 18,874,368-bits QDR(Quad Data Rate) Synchronous Pipelined Burst SRAMs.

They are organized as 524,288 words by 36bits for K7Q163682A and 1,048,576 words by 18 bits for K7Q161882A.

The QDR operation is possible by supporting DDR read and write operations through separate data output and input ports

with the same cycle. Memory bandwidth is maxmized as data can be transfered into sram

on every rising edge of K and K, and transfered out of sram on every rising edge of C and C.

And totally independent read and write ports eliminate the need for high speed bus turn around.

Address, data inputs, and all control signals are synchronized to the input clock ( K or K ).

Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high,

the data outputs are synchronized to the input clocks ( K and K ).

Read address is registered on rising edges of the input K clocks, and write address is

registered on rising edges of the input K clocks.

Common address bus is used to access address both for read and write operations.

The internal burst counter is fiexd to 2-bit sequential for both read and write operations.

Synchronous pipeline read and early write enable high speed operations.

Simple depth expansion is accomplished by using R and W for port selection.

Byte write operation is supported with BW

and BW

( BW

and BW

3 )

pins.

IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoriing package pads attachment status with system.

The K7Q163682A and K7Q161882A are implemented with SAMSUNG's high performance 6T CMOS technology and is available

in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.

Read Operations

Read cycles are initiated by activating R at the rising edge of the positive input clock K.

Address is presented and stored in the read address register synchronized with K clock.

For 2-bit burst DDR operation, it will access two 36-bit or 18-bit data words with each read command.

The first pipelined data is transfered out of the device triggered by C clock following next K clock rising edge.

Next burst data is triggered by the rising edge of following C clock rising edge.

Continuous read operations are initiated with K clock rising edge.

And pipelined data are transferred out of device on every rising edge of both C and C clocks.

In case C and C tied to high, output data are triggered by K and K instead of C and C.

When the R is disabled after a read operation, the K7Q163682A and K7Q161882A will first complete burst read operation

before entering into deselect mode at the next K clock rising edge.

Then output drivers disabled automatically to high impedance state.

-5-

July 2002

Rev 1.0

K7Q161882 Related Products

	K7Q161882	K7Q161882A	K7Q163682A
Description	512Kx36 & 1Mx18 QDR b2 SRAM	512Kx36 & 1Mx18 QDR b2 SRAM	512Kx36 & 1Mx18 QDR b2 SRAM

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