PMC
FEATURES
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Single Power Supply Operation
Low voltage range: 3.0 V - 3.6 V
Standard Intel Firmware Hub/LPC Inter-
face
Read compatible to Intel
®
82802 Firmware
Hub devices
Conforms to Intel LPC Interface Specification
Revision 1.1
Memory Configuration
Pm49FL002: 256K x 8 (2 Mbit)
Pm49FL004: 512K x 8 (4 Mbit)
Cost Effective Sector/Block Architecture
Pm49FL002: Sixty-four uniform 4 Kbyte
sectors, or sixteen uniform 16 Kbyte blocks
(sector group)
Pm49FL004: One hundred and twenty-eight
uniform 4 Kbyte sectors, or eight uniform 64
Kbyte blocks (sector group)
Pm49FL002 / Pm49FL004
2 Mbit / 4 Mbit 3.3 Volt-only Firmware Hub/LPC Flash Memory
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Firmware HUB (FWH)/Low Pin Count
(LPC) Mode
33 MHz synchronous operation with PCI bus
5-signal communication interface for in-
system read and write operations
Standard SDP Command Set
Data# Polling and Toggle Bit features
Register-based read and write protection for
each block (FWH mode only)
4 ID pins for multiple Flash chips selection
(FWH mode only)
5 GPI pins for General Purpose Input Register
TBL# pin for hardware write protection to Boot
Block
WP# pin for hardware write protection to whole
memory array except Boot Block
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Address/Address Multiplexed (A/A Mux)
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Mode
11-pin multiplexed address and 8-pin data I/O
interface
Supports fast programming on EPROM
programmers
Standard SDP Command Set
Data# Polling and Toggle Bit features
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Top Boot Block
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Pm49FL002: 16 Kbyte top Boot Block
Pm49FL004: 64 Kbyte top Boot Block
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Automatic Erase and Program Operation
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Build-in automatic program verification for
extended product endurance
Typical 25 µs/byte programming time
Typical 50 ms sector/block/chip erase time
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Lower Power Consumption
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Typical 2 mA active read current
Typical 7 mA program/erase current
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Two Configurable Interfaces
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In-System hardware interface: Auto detection
of Firmware Hub (FWH) or Low Pin Count
(LPC) memory cycle for in-system read and
write operations
Address/Address-Multiplexed (A/A Mux)
interface for programming on EPROM Pro-
grammers during manufacturing
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High Product Endurance
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Guarantee 100,000 program/erase cycles per
single sector (preliminary)
Minimum 20 years data retention
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Compatible Pin-out and Packaging
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32-pin (8 mm x 14 mm) VSOP
32-pin PLCC
Optional lead-free (Pb-free) package
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Hardware Data Protection
Programmable Microelectronics Corp.
PMC and P-Flash are registered trademark of Programmable Microelectronics Corporation.
Intel is a registered trademark of Intel Corporation.
1
Issue Date: December, 2003 Rev:1.4
PMC
GENERAL DESCRIPTION
Pm49FL002 / 004
The Pm49FL002/004 are 2 Mbit/4 Mbit 3.3 Volt-only Flash Memories used as BIOS in PCs and Notebooks. These
devices are designed to use a single low voltage, ranging from 3.0 Volt to 3.6 Volt, power supply to perform in-
system or off-system read, erase and program operations. The 12.0 Volt V
PP
power supply are not required for the
program and erase operations of devices. The devices conform to Intel
®
Low Pin Count (LPC) Interface specification
revision 1.1 and also read-compatible with Intel 82802 Firmware Hub (FWH) for most PC and Notebook applica-
tions. The Pm49FL002/004 support two configurable interfaces: In-system hardware interface which can automatic
detect the FWH or LPC memory cycle for in-system read and write operations, and Address/Address Multiplexed
(A/A Mux) interface for fast manufacturing on EPROM Programmers. These devices are designed to work with both
Intel Family chipset and Non-Intel Family Chipset platforms, it will provide PC and Notebook manufacturers great
flexibility and simplicity for design, procurement, and material inventory.
The memory array of Pm49FL002 is divided into uniform 4 Kbyte sectors, or uniform 16 Kbytes blocks (sector
group - consists of four adjecent sectors). The memory array of Pm49FL004 is divided into uniform 4 Kbyte sectors,
or uniform 64 Kbyte blocks (sector group - consists of sixteen adjecent sectors). The sector or block erase feature
allows users to flexibly erase a memory area as small as 4 Kbyte or as large as 64 Kbyte by one single erase
operation without affecting the data in others. The chip erase feature allows the whole memory to be erased in one
single erase operation. The devices can be programmed on a byte-by-byte basis after performing the erase opera-
tion.
The program operation of Pm49FL002/004 is executed by issuing the program command code into command
register. The internal control logic automatically handles the programming voltage ramp-up and timing. The erase
operation of the devices is executed by issuing the sector, block, or chip erase command code into command
register. The internal control logic automatically handles the erase voltage ramp-up and timing. The preprogramming
on the array which has not been programmed is not required before an erase operation. The devices offer Data#
Polling and Toggle Bit functions in FWH/LPC and A/A Mux modes, the progress or completion of program and
erase operations can be detected by reading the Data# Polling on I/O7 or Toggle Bit on I/O6.
The Pm49FL002 has a 16 Kbyte top boot block which can be used to store user security data and code. The
Pm49FL004 has a 64 Kbyte top boot block. The boot block can be write protected by a hardware method controlled
by the TBL# pin or a register-based protection turned on/off by the Block Locking Registers (FWH mode only). The
rest of blocks except boot block in the devices also can be write protected by WP# pin or Block Locking Registers
(FWH mode only).
The Pm49FL002/004 are manufactured on PMC’s advanced nonvolatile technology, P-FLASH™. The devices are
offered in 32-pin VSOP and PLCC packages with optional environmental friendly lead-free package.
Programmable Microelectronics Corp.
2
Issue Date: December, 2003 Rev: 1.4
PMC
CONNECTION DIAGRAMS
FWH
RST#
GPI2
GPI3
NC
CLK
GPI4
V
CC
Pm49FL002 / 004
A/A Mux LPC
RST# RST#
GPI2
GPI3
R/C# CLK
FWH
GPI1
GPI0
WP#
TBL#
ID3
ID2
ID1
ID0
FWH0
LPC
GPI1
GPI0
WP#
TBL#
RES
RES
RES
RES
LAD0
A/A Mux
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
5
6
7
8
9
10
11
12
13
14
A/A Mux
I/O1
15
I/O2
16
GND
17
I/O3
18
19
I/O5
20
I/O6
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
NC
A10
V
CC
A8
A9
GPI4
V
CC
NC
A/A Mux
IC
GND
NC
NC
V
CC
OE#
WE#
NC
I/O7
LPC
IC
GND
NC
NC
V
CC
INIT#
FWH
IC
GND
NC
NC
V
CC
INIT#
LFRAME# FWH4
NC
RES
NC
RES
LAD1
I/O4
RES
RES
LAD2
LAD3
FWH2
GND
GND
FWH1
RES
RES
32-PIN PLCC
FWH3
FWH
RES
RES
LPC
FWH
LPC
A/A Mux
A/A Mux
LPC
FWH
V
CC
NC
NC
GND
IC
GPI4
CLK
V
CC
NC
RST#
GPI3
GPI2
GPI1
GPI0
WP#
TBL#
V
C C
NC
NC
GND
IC
GPI4
CLK
V
C C
NC
RST#
GPI3
GPI2
GPI1
GPI0
WP#
TBL#
V
CC
NC
NC
GND
IC
A10
R/C#
V
CC
NC
RST#
A9
A8
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
WE#
NC
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
INIT#
LFRAME#
NC
RES
RES
RES
RES
LAD3
GND
LAD2
LAD1
LAD0
RES
RES
RES
RES
INIT#
FWH4
NC
RES
RES
RES
RES
FWH3
GND
FWH2
FWH1
FWH0
ID0
ID1
ID2
ID3
32-PIN (8mm x 14mm) VSOP
Programmable Microelectronics Corp.
3
Issue Date: December, 2003 Rev: 1.4
PMC
PRODUCT ORDERING INFORMATION
Pm49FL00x
T
-33
J C E
Pm49FL002 / 004
Environmental Attribute
E = Lead-free (Pb-free) Package
Blank = Standard Package
Temperature Range
C = Commercial (0°C to +70°C)
Package Type
J = 32-pin Plastic J-Leaded Chip Carrier (32J)
V = 32-pin (8 mm x 14 mm) VSOP (32V)
Speed Option
Boot Block Location
T = Top Boot Block
PMC Device Number
Pm49FL002 (2 Mbit)
Pm49FL004 (4 Mbit)
Part Number
Pm49FL002T-33JCE
MHz
Boot Block
Location
P ackag e
Temperature
R an g e
32J
Pm49FL002T-33JC
33
Pm49FL002T-33VCE
32V
Pm49FL002T-33VC
Pm49FL004T-33JCE
32J
Pm49FL004T-33JC
33
Pm49FL004T-33VCE
32V
Pm49FL004T-33VC
Top
Commercial
(0°C to +70°C)
Top
Commercial
(0°C to +70°C)
Programmable Microelectronics Corp.
4
Issue Date: December, 2003 Rev: 1.4
PMC
PIN DESCRIPTIONS
SYMB OL
TYPE
Interface
PP
X
FWH
LP C
D ESC R IPTION
Pm49FL002 / 004
A[10:0]
I
Address Inputs: For i nputi ng the multi plex addresses and commands i n
PP mode. Row and column addresses are latched duri ng a read or
wri te cycle controlled by R/C # pi n.
Row/C olumn Select: T i ndi cate the row or column address i n PP
o
mode. When thi s pi n goes low, the row address i s latched. When thi s
pi n goes hi gh, the column address i s latched.
D ata Inputs/Outputs: Used for A/A Mux mode only, to i nput
command/data duri ng wri te operati on and to output data duri ng read
operati on. The data pi ns float to tri -state when OE# i s di sabled.
Wri te Enable: Acti vate the devi ce for wri te operati on. WE# i s acti ve low.
Output Enable: C ontrol the devi ce's output buffers duri ng a read cycle.
OE# i s acti ve low.
Interface C onfi gurati on Select: Thi s pi n determi nes whi ch mode i s
selected. When pulls hi gh, the devi ce enters i nto A/A Mux mode. When
pulls low, FWH/LPC mode i s selected. Thi s pi n must be setup duri ng
power-up or system reset, and stays no change duri ng operati on. Thi s
pi n i s i nternally pulled down wi th a resi stor between 20-100 K
Ω.
Reset: T reset the operati on of the devi ce and return to standby mode.
o
Ini ti ali ze: Thi s i s a second reset pi n for i n-system use. INIT# or RST# pi n
pulls low wi ll i ni ti ate a devi ce reset.
FWH/LPC General Purpose Inputs: Used to set the GPI_REG for
system desi gn purpose only. The value of GPI_REG can be read
through FWH i nterface. These pi ns should be set at desi red state
before the start of the PC I clock cycle for read operati on and should
remai n no change unti l the end of the read cycle. Unused GPI pi ns must
not be floated.
T p Block Lock: When pulls low, i t enables the hardware wri te protecti on
o
for top boot block. When pulls hi gh, i t di sables the hardware wri te
protecti on.
Wri te Protect: When pulls low, i t enables the hardware wri te protecti on
to the memory array except the top boot block. When pulls hi gh, i t
di sables hardware wri te protecti on.
FWH Address and D ata: The major I/O pi ns for transmi tti ng data,
addresses and command code i n FWH mode.
FWH Input: T i ndi cate the start of a FWH memory cycle operati on.
o
Also used to abort a FHW memory cycle i n progress.
X
X
X
X
LPC Address and D ata: The major I/O pi ns for transmi tti ng data,
addresses and command code i n LPC mode.
LPC Frame: T i ndi cate the start of a LPC memory cycle operati on.
o
Also used to abort a LPC memory cycle i n progress.
FWH/LPC C lock: T provi de a synchronous clock for FWH and LPC
o
mode operati ons.
Identi fi cati on Inputs: These four pi ns are part of the mechani sm that
allows multi ple FWH devi ces to be attached to the same bus. The
strappi ng of these pi ns i s used to i denti fy the component. The boot
devi ce must have ID [3:0] = 0000b and i t i s recommended that all
subsequent devi ces should use sequenti al up-count strappi ng. These
pi ns are i nternally pulled-down wi th a resi stor between 20-100 K
Ω.
X
X
X
X
D evi ce Power Supply
Ground
No C onnecti on
Reserved: Reserved functi on pi ns for future use.
R/C #
I
X
I/O[7:0]
WE#
OE#
I/O
I
I
X
X
X
IC
I
X
X
X
RST#
INIT#
I
I
X
X
X
X
X
GPI[4:0]
I
X
X
TBL#
I
X
X
WP#
I
X
X
FWH[3:0]
FWH4
LAD [3:0]
LFRAME#
C LK
I/O
I
I/O
I
I
X
X
ID [3:0]
I
X
V
CC
GND
NC
RES
X
X
X
X
X
X
X
Note: I = Input, O = Output
Programmable Microelectronics Corp.
5
Issue Date: December, 2003 Rev: 1.4
DSP and ARM Processors
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