Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays
(18
×
42
×
10)
PLS153/A
DESCRIPTION
The PLS153 and PLS153A are two-level
logic elements, consisting of 42 AND gates
and 10 OR gates with fusible link connections
for programming I/O polarity and direction.
All AND gates are linked to 8 inputs (I) and
10 bidirectional I/O lines (B). These yield
variable I/O gate configurations via 10
direction control gates (D), ranging from 18
inputs to 10 outputs.
On-chip T/C buffers couple either True (I, B)
or Complement (I, B) input polarities to all
AND gates, whose outputs can be optionally
linked to all OR gates. Their output polarity, in
turn, is individually programmable through a
set of EX-OR gates for implementing
AND/OR or AND/NOR logic functions.
The PLS153 and PLS153A are
field-programmable, enabling the user to
quickly generate custom patterns using
standard programming equipment.
FEATURES
•
Field-Programmable (Ni-Cr links)
•
8 inputs
•
42 AND gates
•
10 OR gates
•
10 bidirectional I/O lines
•
Active-High or -Low outputs
•
42 product terms:
–
32 logic terms
–
10 control terms
PIN CONFIGURATIONS
N Package
I
0
I
1
I
2
I
3
I
4
I
5
I
6
I
7
B
0
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
V
CC
B
9
B
8
B
7
B
6
B
5
B
4
B
3
B
2
B
1
•
I/O propagation delay:
–
PLS153: 40ns (max)
–
PLS153A: 30ns (max)
GND 10
•
Input loading: –100
µ
A (max)
•
Power dissipation: 650mW (typ)
•
3-State outputs
•
TTL compatible
APPLICATIONS
N = Plastic DIP (300mil-wide)
A Package
I
2
3
I
3
I
4
I
5
I
6
I
7
4
5
6
7
8
9
10
11
12
13
I
1
2
I
0
V
CC
B
9
1
20
19
18
17
16
15
14
B
8
B
7
B
6
B
5
B
4
•
Random logic
•
Code converters
•
Fault detectors
•
Function generators
•
Address mapping
•
Multiplexing
ORDERING INFORMATION
DESCRIPTION
20-Pin Plastic Dual In-Line, 300mil-wide
20-Pin Plastic Leaded Chip Carrier
ORDER CODE
PLS153N, PLS153AN
PLS153A, PLS153AA
B
0
GND B
1
B
2
B
3
A = Plastic Leaded Chip Carrier
SP00274
DRAWING NUMBER
0408B
0400E
October 22, 1993
1
853–0311 11164
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays
(18
×
42
×
10)
PLS153/A
LOGIC DIAGRAM
(LOGIC TERMS–P)
I0
I1
I2
I3
I4
I5
I6
I7
1
2
3
4
5
6
7
8
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
(CONTROL TERMS)
S
9
X
9
X
8
X
7
X
6
X
5
X
4
X
3
X
2
X
1
31
24 23
16 15
8 7
0
X
0
S
8
S
7
S
6
S
5
S
4
S
3
S
2
S
1
S
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
19 B9
18 B8
17 B7
16 B6
15 B5
14 B4
13 B3
12 B2
11 B1
9 B0
NOTES:
1. All programmed ‘AND’ gate locations are pulled to logic “1”.
2. All programmed ‘OR’ gate locations are pulled to logic “0”.
3.
Programmable connection.
SP00276
October 22, 1993
2
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays
(18
×
42
×
10)
PLS153/A
FUNCTIONAL DIAGRAM
P
31
I
0
P
0
D
0
D
9
I
7
B
0
B
9
S
9
X
9
B
9
S
0
X
0
B
0
SP00277
ABSOLUTE MAXIMUM RATINGS
1
RATINGS
SYMBOL
V
CC
V
IN
V
OUT
I
IN
I
OUT
T
amb
T
stg
PARAMETER
Supply voltage
Input voltage
Output voltage
Input currents
Output currents
Operating temperature range
Storage temperature range
0
–65
–30
MIN
MAX
+7
+5.5
+5.5
+30
+100
+75
+150
UNIT
V
DC
V
DC
V
DC
mA
mA
°C
°C
NOTES:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This
is a stress rating only. Functional operation at these or any other condition above those
indicated in the operational and programming specification of the device is not implied.
October 22, 1993
3
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays
(18
×
42
×
10)
PLS153/A
LOGIC FUNCTION
TYPICAL PRODUCT TERM:
Pn = A B C D . . .
THERMAL RATINGS
TEMPERATURE
Maximum junction
Maximum ambient
Allowable thermal rise
ambient to junction
150°C
75°C
75°C
⋅ ⋅ ⋅ ⋅
TYPICAL LOGIC FUNCTION:
AT OUTPUT POLARITY = H
Z = P0 + P1 + P2 . . .
AT OUTPUT POLARITY = L
Z = P0 + P1 + P2 + . . .
Z = P0 P1 P2 . . .
⋅
⋅
⋅
NOTES:
1. For each of the 10 outputs, either function Z
(Active-High) or Z (Active-Low) is available, but not
both. The desired output polarity is programmed via
the Ex-OR gates.
2. Z, A, B, C, etc. are user defined connections to fixed
inputs (I) and bidirectional pins (B).
SP00275
The PLS153/A devices are also processed to
military requirements for operation over the
military temperature range. For specifications
and ordering information consult the Philips
Semiconductors Military Data Handbook.
DC ELECTRICAL CHARACTERISTICS
0°C
≤
T
amb
≤
+75°C, 4.75V
≤
V
CC
≤
5.25V
LIMITS
SYMBOL
Input voltage
2
V
IL
V
IH
V
IC
Low
High
Clamp
3
V
CC
= MIN
V
CC
= MAX
V
CC
= MIN, I
IN
= –12mA
V
CC
= MIN
V
OL
V
OH
Low
4
High
5
I
OL
= 15mA
I
OH
= –2mA
V
CC
= MAX
I
IL
I
IH
Low
High
V
IN
= 0.45V
V
IN
= 5.5V
V
CC
= MAX
I
O(OFF)
I
OS
I
CC
Capacitance
V
CC
= 5V
C
IN
C
B
Input
I/O
V
IN
= 2.0V
V
B
= 2.0V
8
15
pF
pF
Hi-Z state
8
Short circuit
3, 5, 6
V
CC
supply current
7
V
OUT
= 5.5V
V
OUT
= 0.45V
V
OUT
= 0V
V
CC
= MAX
–15
130
80
–140
–70
155
mA
mA
µA
–100
40
µA
µA
2.4
0.5
V
V
2.0
–0.8
–1.2
0.8
V
V
V
PARAMETER
TEST CONDITIONS
MIN
TYP
1
MAX
UNIT
Output voltage
2
Input current
9
Output current
NOTES:
1. All typical values are at V
CC
= 5V, T
amb
= +25°C.
2. All voltage values are with respect to network ground terminal.
3. Test one at a time.
4. Measured with +10V applied to I
7
.
5. Measured with +10V applied to I
0–7
. Output sink current is supplied through a resistor to V
CC
.
6. Duration of short circuit should not exceed 1 second.
7. I
CC
is measured with I
0
, I
1
at 0V, I
2
– I
7
and B
0–9
at 4.5V.
8. Leakage values are a combination of input and output leakage.
9. I
IL
and I
IH
limits are for dedicated inputs only (I
0
– I
7
).
October 22, 1993
4
Philips Semiconductors Programmable Logic Devices
Product specification
Programmable logic arrays
(18
×
42
×
10)
PLS153/A
AC ELECTRICAL CHARACTERISTICS
0°C
≤
T
amb
≤
+75°C, 4.75V
≤
V
CC
≤
5.25V, R
1
= 300Ω, R
2
= 390Ω
LIMITS
SYMBOL
PARAMETER
FROM
TO
TEST
CONDITION
t
PD
t
OE
t
OD
Propagation delay
Output enable
2
Output disable
2
Input
±
Input
±
Input
±
Output
±
Output –
Output +
C
L
= 30pF
C
L
= 30pF
C
L
= 5pF
MIN
PLS153
TYP
1
30
25
25
MAX
40
35
35
MIN
PLS153A
TYP
1
20
20
20
MAX
30
30
30
ns
ns
ns
UNIT
NOTES:
1. All typical values are at V
CC
= 5V, T
amb
= +25°C.
2. For 3-State output; output enable times are tested with C
L
= 30pF to the 1.5V level, and S
1
is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with C
L
= 5pF. High-to-High impedance tests are made to an output
voltage of V
T
= (V
OH
– 0.5V) with S
1
open, and Low-to-High impedance tests are made to the V
T
= (V
OL
+ 0.5V) level with S
1
closed.
3. All propagation delays are measured and specified under worst case conditions.
VOLTAGE WAVEFORMS
+3.0V
90%
TIMING DEFINITIONS
SYMBOL
t
PD
10%
PARAMETER
Propagation delay between
input and output.
Delay between input change
and when output is off (Hi-Z
or High).
Delay between input change
and when output reflects
specified output level.
0V
5ns
+3.0V
90%
t
R
t
F
5ns
t
OD
t
OE
10%
0V
5ns
5ns
MEASUREMENTS:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
Input Pulses
SP00017
TEST LOAD CIRCUIT
V
CC
+5V
S
1
C
1
C
2
I
0
B
Y
R
1
INPUTS
I
7
B
W
DUT
R
2
C
L
B
X
GND
B
Z
OUTPUTS
NOTE:
C
1
and C
2
are to bypass V
CC
to GND.
SP00278
October 22, 1993
5
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