PLL602-14
192MHz – 400MHz Low Phase Noise LVDS XO (12 – 25MHz Crystal)
FEATURES
•
•
•
•
•
•
•
Low phase noise output for the 192MHz to
400MHz range (-134 dBc at 10kHz offset).
LVDS output.
12 to 25MHz crystal input.
Integrated crystal load capacitor: no external
load capacitor required.
Output Enable selector.
3.3V operation.
Available in 16 Pin TSSOP.
PIN CONFIGURATION
VDD
VDD
XIN
XOUT
OE^
N/C
GND
GND
1
2
16
15
VDD
GND_BUF
CLKBAR
VDD_BUF
CLK
GND_BUF
GND
GND
PLL 602-14
3
4
5
6
7
8
14
13
12
11
10
9
Note: ^ denotes internal pull up
DESCRIPTION
The PLL602-14 is a monolithic low jitter and low
phase noise (-134dBc/Hz @ 10kHz offset) XO IC
with LVDS output, for 192MHz to 400MHz output
range. It provides a low phase noise reference
frequency using a low cost crystal.
The chip delivers an output frequency of F
XIN
x 16.
This makes the PLL602-14 ideal for a wide range of
applications.
F
OUT
= F
X IN
x 16
OE (Pin 5)
0
1 (Default)
Output State
Tri-state
Output enabled
BLOCK DIAGRAM
VCO
Divider
Reference
Divider
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
CLKBAR
CLK
XIN
XOUT
XTAL
OSC
OE
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/03/04 Page 1
PLL602-14
192MHz – 400MHz Low Phase Noise LVDS XO (12 – 25MHz Crystal)
PIN DESCRIPTIONS
Name
VDD
XIN
XOUT
OE
N/C
GND
GND_BUF
CLK
VDD_BUF
CLKB
Number
1,2,16
3
4
5
6
7,8,9,10
11,15
12
13
14
Type
P
I
I
I
-
P
P
O
P
O
Description
Power supply.
Crystal input. See Crystal Specifications on page 2.
Crystal output. See Crystal Specifications on page 2.
Output enable input. Disables (tri-state) output when low. Internal pull-up
enables output by default if pin is not connected to low.
Not connected.
Ground.
Ground for output buffers.
True clock output.
Power supply for output buffers.
Complementary clock output.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS
Crystal Resonator Frequency
Crystal Loading Rating
Recommended ESR
SYMBOL
F
XIN
C
L (xtal)
R
E
CONDITIONS
Parallel Fundamental Mode
AT cut
MIN.
12
TYP.
20
MAX.
25
30
UNITS
MHz
pF
Ω
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/03/04 Page 2
PLL602-14
192MHz – 400MHz Low Phase Noise LVDS XO (12 – 25MHz Crystal)
3. General Electrical Specifications
PARAMETERS
Supply Current, Dynamic
(with Loaded Outputs)
Operating Voltage
Output Clock Duty Cycle
Short Circuit Current
SYMBOL
I
DD
V
DD
LVDS
CONDITIONS
MIN.
TYP.
MAX.
60
UNITS
mA
V
%
mA
@ 1.25V (LVDS)
2.97
45
50
±50
3.63
55
4. Jitter and Phase Noise Specification
PARAMETERS
Period jitter RMS
Accumulated jitter RMS
Phase
Phase
Phase
Phase
Noise
Noise
Noise
Noise
relative
relative
relative
relative
to
to
to
to
carrier
carrier
carrier
carrier
CONDITIONS
With capacitive decoupling
between VDD and GND.
With capacitive decoupling
between VDD and GND. Over
10,000 cycles.
311MHz @100Hz offset
311MHz @1kHz offset
311MHz @10kHz offset
311MHz @100kHz offset
MIN.
TYP.
5
11
-90
-114
-134
-134
MAX.
UNITS
ps
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/03/04 Page 3
PLL602-14
192MHz – 400MHz Low Phase Noise LVDS XO (12 – 25MHz Crystal)
5. LVDS Electrical Characteristics
PARAMETERS
Output Differential Voltage
V
DD
Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
Offset Magnitude Change
Power-off Leakage
Output Short Circuit Current
SYMBOL
V
OD
∆V
OD
V
OH
V
OL
V
OS
∆V
OS
I
OXD
I
OSD
CONDITIONS
MIN.
247
-50
TYP.
355
1.4
1.1
1.2
3
±1
-5.7
MAX.
454
50
1.6
1.375
25
±10
-8
UNITS
mV
mV
V
V
V
mV
uA
mA
R
L
= 100
Ω
(see figure)
0.9
1.125
0
V
out
= V
DD
or GND
V
DD
= 0V
6. LVDS Switching Characteristics
PARAMETERS
Differential Clock Rise Time
Differential Clock Fall Time
LVDS Levels Test Circuit
OUT
SYMBOL
t
r
t
f
CONDITIONS
R
L
= 100
Ω
C
L
= 10 pF
(see figure)
MIN.
0.2
0.2
TYP.
0.7
0.7
MAX.
1.0
1.0
UNITS
ns
ns
LVDS Switching Test Circuit
OUT
50Ω
C
L
= 10pF
V
OD
V
OS
V
DIFF
R
L
= 100Ω
50Ω
C
L
= 10pF
OUT
OUT
LVDS Transistion Time Waveform
OUT
0V (Differential)
OUT
80%
V
DIFF
20%
0V
80%
20%
t
R
t
F
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/03/04 Page 4
PLL602-14
192MHz – 400MHz Low Phase Noise LVDS XO (12 – 25MHz Crystal)
PACKAGE INFORMATION
16 PIN TSSOP ( mm )
Symbol
A
A1
B
C
D
E
H
L
e
Min.
Max.
-
1.20
0.05
0.15
0.19
0.30
0.09
0.20
4.90
5.10
4.30
4.50
6.40 BSC
0.45
0.75
0.65 BSC
E
H
D
A
A1
e
B
C
L
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL602-14 S C
PART NUMBER
TEMPERATURE
C=COMMERCIAL
I=INDUSTRAL
PACKAGE TYPE
O=TSSOP
Order Number
PLL602-14OC-R
PLL602-14OC
Marking
P602-14OC
P602-14OC
Package Option
TSSOP - Tape and Reel
TSSOP – Tube
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY:
PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/03/04 Page 5
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