High Speed Super Low Power SRAM
512k word x 8 bit
CS18LV40963
DESCRIPTION
The CS18LV40963 is a high performance, high speed, low power CMOS Static
Random Access Memory organized as 524,288 words by 8 bits and operates from a wide
range of 2.7 to 3.6V supply voltage. Advanced CMOS technology and circuit techniques
provide both high speed and low power features with a typical CMOS standby current of
0.20uA and maximum access time of 50/55/70ns in 3.0V operation. Easy memory
expansion is provided by an active LOW chip enable (/CE) and active LOW output enable
(/OE) and three-state output drivers.
The CS18LV40963 has an automatic power down feature, reducing the power
consumption significantly when chip is deselected. The CS18LV40963 is available in
JEDEC standard 32-pin TSOP (I) (8x20mm), TSOP (II) (400 mil), SOP (450 mil), STSOP
(8x13.4 mm) and 36-ball CSP 6x8mm package..
FEATURES
Low operation voltage : 2.7 ~ 3.6V
Ultra low power consumption :
(Vcc = 3.0V)
3mA＠1MHz (Max.) operating current
0.20 uA (Typ.) CMOS standby current
High speed access time : 50~70ns (Max.) at Vcc = 3.0V.
Automatic power down when chip is deselected.
Three state outputs and TTL compatible
Fully static operation.
Data retention supply voltage as low as 1.5V.
Easy expansion with /CE and /OE options.
Copyright
2004-March Chiplus Semiconductor Corp. All rights reserved.
Rev. 1.2
P1
High Speed Super Low Power SRAM
512k word x 8 bit
CS18LV40963
Standby (Typ.)
Package Type
32 SOP
Product Family
Part No.
CS18LV40963CC
CS18LV40963DC
CS18LV40963EC
CS18LV40963FC
CS18LV40963KC
CS18LV40963CI
CS18LV40963DI
CS18LV40963EI
CS18LV40963FI
CS18LV40963KI
Note: Green package part no, sees order information.
-40~85
o
C
2.7~3.6
50/55/70
0.30 uA
(Vcc= 3.3V)
0~70
o
C
2.7~3.6
50/55/70
0.20 uA
(Vcc = 3.3V)
Operating Temp Vcc. Range Speed (ns)
32 STSOP
32 TSOP (I)
32 TSOP (II)
36 CSP-0608
32 SOP
32 STSOP
32 TSOP (I)
32 TSOP (II)
36 CSP-0608
PIN CONFIGURATIONS
32 SOP 450 mil
32 TSOP(II) 400 mil
32 STSOP 8x13.4mm
32 TSOP(I) 8x20mm
Copyright
2004-March Chiplus Semiconductor Corp. All rights reserved.
Rev. 1.2
P2
High Speed Super Low Power SRAM
512k word x 8 bit
CS18LV40963
36 Ball CSP – Top View
BLOCK DIAGRAM
Copyright
2004-March Chiplus Semiconductor Corp. All rights reserved.
Rev. 1.2
P3
High Speed Super Low Power SRAM
512k word x 8 bit
CS18LV40963
Function
PIN DESCRIPTIONS
Name
A0-A18
Address Input
/CE
Chip Enable Input
These 19 address inputs select one of the 524,288 x 8-bit words
in the RAM.
/CE is active LOW Chip enables must be active when data read
from or write to the device. if chip enable is not active, the device
is deselected and is in a standby power mode. The DQ pins will
be in the high impedance state when the device is deselected.
The write enable input is active LOW and controls read and
write operations. With the chip selected, when /WE is HIGH and
/OE is LOW, output data will be present on the DQ pins; when
/WE is LOW, the data present on the DQ pins will be written into
the selected memory location.
The output enable input is active LOW. If the output enable is
active while the chip is selected and the write enable is inactive,
data will be present on the DQ pins and they will be enabled.
The DQ pins will be in the high impedance state when /OE is
inactive.
These 8 bi-directional ports are used to read data from or write
data into the RAM.
Power Supply
Ground
/WE
Write Enable Input
/OE
Output Enable Input
DQ0-DQ7
Data Input/Output
Ports
Vcc
Gnd
Copyright
2004-March Chiplus Semiconductor Corp. All rights reserved.
Rev. 1.2
P4
High Speed Super Low Power SRAM
512k word x 8 bit
CS18LV40963
DQ0~7
High Z
High Z
D
OUT
D
IN
Vcc Current
I
CCSB
, I
CCSB1
I
CC
I
CC
I
CC
TRUTH TABLE
MODE
Not Selected
Output
Disabled
Read
Write
/CE
H
X
L
L
L
/WE
X
X
H
H
L
/OE
X
X
H
L
X
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
V
TERM
T
BIAS
T
STG
P
T
I
OUT
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Rating
-0.5 to Vcc+0.5
-40 to +125
-60 to +150
1.0
20
Unit
V
O
C
C
O
W
mA
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Copyright
2004-March Chiplus Semiconductor Corp. All rights reserved.
Rev. 1.2
P5
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