ECS-240-20-28AX-CGL-TR datasheet, PDF

Datasheet> All Categories > Passive components> Crystal/resonator> ECS-240-20-28AX-CGL-TR

ECS-240-20-28AX-CGL-TR: DescriptionParallel - Fundamental Quartz Crystal,; CategoryPassive components Crystal/resonator; File Size578KB，2 Pages; ManufacturerECS; Websitehttp://www.ecsxtal.com/; Environmental Compliance

Download Datasheet Parametric View All

ECS-240-20-28AX-CGL-TR Overview

Parallel - Fundamental Quartz Crystal,

ECS-240-20-28AX-CGL-TR Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	7203320787
package instruction	SMD, 4 PIN
Reach Compliance Code	compliant
YTEOL	6.45
Other features	TR, 12 INCH
Ageing	5 PPM/FIRST YEAR
Crystal/Resonator Type	PARALLEL - FUNDAMENTAL
Drive level	500 µW
frequency stability	0.003%
frequency tolerance	10 ppm
JESD-609 code	e4
load capacitance	20 pF
Installation features	SURFACE MOUNT
Nominal operating frequency	24 MHz
Maximum operating temperature	70 °C
Minimum operating temperature	-10 °C
physical size	L12.5XB4.85XH5.0 (mm)/L0.492XB0.191XH0.197 (inch)
Series resistance	30 Ω
surface mount	YES
Terminal surface	Silver (Ag)

Preview

Download Datasheet

View All

CSM-4AX

SMD CRYSTAL

The CSM-4AX is an excellent choice for a low cost SMD crystal. The CSM-4AX (28AX)

has a case height of 5.0 mm Max. in a resistance weld metal package. Lower profile

package height of 4.0 mm Max. is available with the (28ALX)

package.

Request a Sample

CSM-4AX SMD CRYSTAL

OPERATING CONDITIONS / ELECTRICAL CHARACTERISTICS

PARAMETERS

Frequency

Mode of Oscillation

Frequency Tolerance*

Frequency Stability*

Shunt Capacitance

Load Capacitance

Drive Level

Operating Temperature*

Storage Temperature

Aging (First Year)

Fundamental

@ +25°C

-10 ~ +70°C

CONDITIONS

MIN

CSM-4AX

TYP

MAX

UNITS

30.000

± 30

± 50

MHz

ppm

μW

°C

ppm

3.57

Specify in P/N

opr

stg

@ +25°C ±3°C

Frequency (MHz)

3.57 ~ 4.999

5.000 ~ 5.999

6.000 ~ 6.999

7.000 ~ 8.999

9.000 ~ 12.999

13.000 ~ 19.999

20.000 ~ 30.000

-10

-55



Cost Effective

Low Profile

Industry Standard Footprint

Pb Free/RoHS Compliant

Series

500

+70

+125

±5

DIMENSIONS (mm)

ESR Ω Max.

200

150

100

Figure 1)

Top, Side, and End

Figure 2)

Suggested land

pattern

PART NUMBERING GUIDE: Example ECS-200-20-28AX-TR

ECS - FREQUENCY ABBREVIATION

LOAD

CAPACITANCE

20 = 20 pF

S = Series

PACKAGE

Tolerance

28AX = 5.0 mm

28ALX = 4.0 mm

Blank = Std

A = ± 25

ppm

J = ± 20

ppm

R = ± 15

ppm

C = ± 10

ppm

AVAILABLE OPTIONS

Stability

Blank= Std

D= ±100 ppm

E = ± 50 ppm

G = ± 30 ppm

H = ± 25 ppm

T = ± 20 ppm †

W = ±15 ppm †

K = ± 10 ppm †

PACKAGING

Temp Range

Blank= Std

L = -10 ~ +70°C

M = -20 ~ +70°C

Y = -30 ~ +85°C

N = -40 ~ +85°C

P = -40 ~ +105°C

S = -40 ~ +125°C

U = -55 ~ +125°C

TR =

Tape

& Reel

1K/Reel

ECS

200 = 20.000 MHz

See P/N Guide

* Specify available options in P/N.

† Contact ECS for availability over extended temp range.

Rev.2017

15351 West 109

Street

Lenexa, KS 66219

Phone: 913.782.7787

Fax: 913.782.6991

www.ecsxtal.com

Recommended Resources

Humidity detection circuit schematic diagram

Z80 clock circuit diagram

Sending and receiving microphone (sensing) interface circuit

L292 driver circuit diagram

555 ventilation fan automatic control circuit

555 non-contact car turning buzzer circuit

Help my classmate: Everyone please give me a thumbs up, thank you! [:$][^o)][8o|][:^)]...; wenchuenyi000 MCU

Ask: Multi-channel audio acquisition design solution: I want to make a set of hardware to realize 8-channel audio acquisition, and transmit it in real time through the network interface on the hardware (with the PC). Can anyone provide technical support?...; yuanwai001 DSP and ARM Processors

Altera series FPGA chip IP core detailed explanation.pdf: Altera series FPGA chip IP core detailed explanation .pdf...; zxopenljx FPGA/CPLD

A question about delay detection: The following code always fails to compile, and the error displayed is: Error (10822): HDL error at test17.vhd(384): couldn't implement registers for assignments on this clock edge The main meaning of...; dandanzhou FPGA/CPLD

[Xilinx Design Q&A] How to control XST insertion into BUFFER?: Answer: 1. Use BUFFER_TYPE constraints. For specific usage, refer to XST USER GUIDE.2. Manually insert BUFG, and then set the number of BUFGs allowed to be used. Then the manually inserted BUFG will h...; eeleader FPGA/CPLD

msp430f147+MAX7219+ENCODER implementation: I originally used LaunchPad to do this project, because after the program was compiled, it exceeded the size of the G2231 Flash ROM, so I rummaged through the cabinets and found the 147PCB I drew myse...; naga568 Microcontroller MCU

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components