K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
DDP 4Gb B-die DDR3 SDRAM Specification
78 FBGA with Lead-Free & Halogen-Free
(RoHS Compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE
CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-
WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-
OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT
GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
Year
2009
- First release
History
Revision History
Revision
1.0
Month
March
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DDP 4Gb DDR3 SDRAM
Table Contents
1.0 Ordering Information ................................................................................................................... 5
2.0 Key Features ................................................................................................................................ 5
3.0 Package pinout/Mechanical Dimension & Addressing ............................................................ 6
3.1 x4 DDP Package Pinout (Top view) : 78ball FBGA Package
.............................................................. 6
3.2 x8 DDP Package Pinout (Top view) : 78ball FBGA Package
.............................................................. 7
3.3 FBGA Package Dimension (x4)
..................................................................................................... 8
3.4 FBGA Package Dimension (x8)
..................................................................................................... 9
4.0 Input/Output Functional Description ....................................................................................... 10
5.0 DDR3 SDRAM Addressing ........................................................................................................ 11
6.0 Absolute Maximum Ratings ...................................................................................................... 12
6.1 Absolute Maximum DC Ratings
................................................................................................... 12
6.2 DRAM Component Operating Temperature Range
......................................................................... 12
7.0 AC & DC Operation Conditions ................................................................................................ 12
7.1 Recommended DC operating Conditions (SSTL_1.5)
..................................................................... 12
8.0 AC & DC Input Measurement Levels ........................................................................................ 13
8.1 AC and DC Logic input levels for single-ended singnals
................................................................ 13
8.2 VREF Tolerances
....................................................................................................................... 14
8.3 AC and DC Logic Input Levels for Ditterential Signals
................................................................... 15
8.3.1 Differential signal definition
................................................................................................ 15
8.3.2 Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS)
.............................. 15
8.3.3 Single-ended requirements for differential signals
................................................................. 16
8.4 Differential Input Cross Point Voltage
.......................................................................................... 17
8.5 Slew Rate Definition for Single Ended Input Signals
...................................................................... 17
8.6 Slew rate definition for Differential Input Signals
........................................................................... 17
9.0 AC and DC Output Measurement Levels ................................................................................. 18
9.1 Single Ended AC and DC Output Levels
....................................................................................... 18
9.2 Differential AC and DC Output Levels
.......................................................................................... 18
9.3 Single Ended Output Slew Rate
................................................................................................... 18
9.4 Differential Output Slew Rate
...................................................................................................... 19
9.5 Reference Load for AC Timing and Output Slew Rate
.................................................................... 19
9.6 Overshoot/Undershoot Specification
........................................................................................... 20
9.6.1 Address and Control Overshoot and Undershoot specifications
............................................. 20
9.6.2 Clock, Data, Strobe and Mask Overshoot and Undershoot specifications
................................. 20
9.7 34 ohm Output Driver DC Electrical Characteristics
....................................................................... 21
................................................................. 22
9.8 On-Die Termination (ODT) Levels and I-V Characteristics
............................................................... 22
9.8.1 ODT DC electrical characteristics
........................................................................................ 23
9.8.2 ODT Temperature and Voltage sensitivity
............................................................................. 24
9.7.1 Output Drive Temperature and Voltage sensitivity
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9.9 ODT Timing Definitions
DDP 4Gb DDR3 SDRAM
.............................................................................................................. 25
................................................................................................. 25
9.9.2 ODT Timing Definition
........................................................................................................ 25
9.9.1 Test Load for ODT Timings
10.0 IDD Specification Parameters and Test Conditions ............................................................. 28
10.1 IDD Measurement Conditions
.................................................................................................... 28
10.2 IDD Specifications definition
..................................................................................................... 30
11.0 DDP 4Gb DDR3 SDRAM B-die IDD Spec Table ..................................................................... 37
12.0 Input/Output Capacitance ....................................................................................................... 38
13.0 Electrical Characteristics and AC timing for DDR3-800 to DDR3-1600 .............................. 39
13.1 Clock specification
............................................................................................................. 39
13.1.1 Definition for tCK (avg)
..................................................................................................... 39
13.1.2 Definition for tCK (abs)
..................................................................................................... 39
13.1.3 Definition for tCH(avg) and tCL(avg)
................................................................................... 39
13.1.4 Definition for note for tJIT(per), tJIT(per,Ick)
........................................................................ 39
...................................................................................... 39
13.1.6 Definition for tERR(nper)
................................................................................................... 39
13.2 Refresh Parameters by Device Density
....................................................................................... 40
13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin
............................................. 40
13.3.1 Speed Bin Table Notes...........................................................................................................................
43
13.1.5 Definition for tJIT(cc), tJIT(cc,Ick)
14.0 Timing Parameters by Speed Grade ...................................................................................... 44
14.1 Jitter Notes
............................................................................................................................. 47
14.2 Timing Parameter Notes
........................................................................................................... 48
14.3 Address / Command Setup, Hold and Derating:
........................................................................... 49
14.4 Data Setup, Hold and Slew Rate Derating:
.................................................................................. 55
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1.0 Ordering Information
[ Table 1 ] Samsung DDP 4Gb DDR3 B-die ordering information table
Organization
1Gx4
512Mx8
DDR3-800 (6-6-6)
K4B4G0446B-MCF7
K4B4G0846B-MCF7
DDR3-1066 (7-7-7)
K4B4G0446B-MCF8
K4B4G0846B-MCF8
DDP 4Gb DDR3 SDRAM
DDR3-1333 (9-9-9)
K4B4G0446B-MCH9
K4B4G0846B-MCH9
Package
78 FBGA
78 FBGA
Note :
1. Speed bin is in order of CL-tRCD-tRP.
2.0 Key Features
[ Table 2 ] DDP 4Gb DDR3 B-die Speed bins
Speed
tCK(min)
CAS Latency
tRCD(min)
tRP(min)
tRAS(min)
tRC(min)
DDR3-800
6-6-6
2.5
6
15
15
37.5
52.5
DDR3-1066
7-7-7
1.875
7
13.125
13.125
37.5
50.625
DDR3-1333
9-9-9
1.5
9
13.5
13.5
36
49.5
Unit
ns
nCK
ns
ns
ns
ns
• JEDEC standard 1.5V ± 0.075V Power Supply
• V
DDQ
= 1.5V ± 0.075V
• 400 MHz f
CK
for 800Mb/sec/pin, 533MHz f
CK
for 1066Mb/sec/pin,
667MHz f
CK
for 1333Mb/sec/pin
• 8 Banks
• Posted CAS
• Programmable CAS Latency(posted CAS): 6, 7, 8, 9, 10
• Programmable Additive Latency: 0, CL-2 or CL-1 clock
• Programmable CAS Write Latency (CWL) = 5 (DDR3-800), 6
(DDR3-1066) and 7 (DDR3-1333)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting
address “000” only), 4 with tCCD = 4 which does not allow seamless
read or write [either On the fly using A12 or MRS]
• Bi-directional Differential Data-Strobe
• Internal(self) calibration : Internal self calibration through ZQ pin
(RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than T
CASE
85°C, 3.9us at
85°C < T
CASE
< 95
°C
• Asynchronous Reset
• Package : 78 balls FBGA - x4/x8
• All of Lead-Free products are compliant for RoHS
• All of products are Halogen-free
The DDP 4Gb DDR3 SDRAM B-die is organized as a 128Mbit x 4 I/Os x
8banks, 64Mbit x 8 I/Os x 8banks. This synchronous device achieves high
speed double-data-rate transfer rates of up to 1333Mb/sec/pin (DDR3-
1333) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM fea-
tures such as posted CAS, Programmable CWL, Internal (Self) Calibra-
tion, On Die Termination using ODT pin and Asynchronous Reset .
All of the control and address inputs are synchronized with a pair of exter-
nally supplied differential clocks. Inputs are latched at the crosspoint of dif-
ferential clocks (CK rising and CK falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-
ion. The address bus is used to convey row, column, and bank address
information in a RAS/CAS multiplexing style. The DDR3 device operates
with a single 1.5V ± 0.075V power supply and 1.5V ± 0.075V V
DDQ
.
The 4Gb DDR3 B-die device is available in 78ball FBGAs(x4/x8).
Note : 1. The functionality described and the timing specifications included
in this data sheet are for the DLL Enabled mode of operation.
Note : This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in “DDR3 SDRAM Device
Operation & Timing Diagram”.
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Rev. 1.0 March 2009
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