K4H510838C
K4H511638C
Industrial
DDR SDRAM
512Mb C-die DDR SDRAM Specification
with Pb-Free
(RoHS compliant)
Industrial Temp. -40 to 85°C
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.6 January 2006
K4H510838C
K4H511638C
Industrial
DDR SDRAM
Table of Contents
1.0 Key Features ...............................................................................................................................4
2.0 Ordering Information ...................................................................................................................4
3.0 Operating Frequencies................................................................................................................4
4.0 Pin Description of TSOP .............................................................................................................5
5.0 Ball Description of FBGA ...........................................................................................................5
6.0 Package Physical Dimension .....................................................................................................6
7.0 Block Diagram (16Mbit x8 / 8Mbit x 16 I/O x4 Banks) ..............................................................7
8.0 Input/Output Function Description ............................................................................................8
9.0 Command Truth Table.................................................................................................................9
10.0 General Description ................................................................................................................10
11.0 Absolute Maximum Rating......................................................................................................10
12.0 DC Operating Conditions ........................................................................................................10
13.0 DDR SDRAM Spec Items & Test Conditions ........................................................................11
14.0 Input/Output Capacitance .......................................................................................................11
15.0 Detailed test condition for DDR SDRAM IDD1 & IDD7A ......................................................12
16.0 DDR SDRAM IDD spec table ..................................................................................................13
17.0 AC Operating Conditions .......................................................................................................14
18.0 AC Overshoot/Undershoot specification for Address and Control Pins............................14
19.0 Overshoot/Undershoot specification for Data, Strobe and Mask Pins ..............................15
20.0 AC Timming Parameters & Specifications ............................................................................16
21.0 System Characteristics for DDR SDRAM ..............................................................................17
22.0 Component Notes ...................................................................................................................18
23.0 System Notes ...........................................................................................................................20
24.0 IBIS : I/V Characteristics for Input and Output Buffers ........................................................21
Rev. 1.6 January 2006
K4H510838C
K4H511638C
Industrial
DDR SDRAM
Year
2005
2005
2005
2005
2006
2006
2007
- Release the Rev. 1.0 spec.
- Added system characteristic for DDR SDRAM specification related DDR333.
- Changed master format.
- Changed tREFI specification from 3.9us to 7.8us
- Changed tDQSQ/tQHS of DDR333 FBGA package from 0.45/0.55 to 0.4/0.5.
- Changed Overshoot/Undershoot SPEC flowing JEDEC description.
- Revised overshoot/undershoot specification following JEDEC SPEC
- Added tPDEX on AC parameter specification
History
Revision History
Revision
1.0
1.1
1.2
1.3
1.4
1.5
1.6
Month
Feb.
Mar.
Jun.
December
May
November
January
Rev. 1.6 January 2006
K4H510838C
K4H511638C
Industrial
DDR SDRAM
1.0 Key Features
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe[DQS] (x4, x8) & [L(U)DQS] (x16)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• DM for write masking only (x4, x8)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
•
Support Industrial Temp (-40 to 85°C)
• Maximum burst refresh cycle : 8
• 66pin TSOP II
Pb-Free
package (x8, x16), 60Ball FBGA
Pb-Free
Package(x8, x16)
•
RoHS compliant for Pb-Free Package
2.0 Ordering Information
Part No.
K4H511638C-UI/PB3
K4H511638C-UI/PB0
K4H510838C-UI/PB3
K4H510838C-UI/PB0
K4H511638C-ZI/PB3
K4H511638C-ZI/PB0
K4H510838C-ZI/PB3
K4H510838C-ZI/PB0
Org.
32M x 16
64M x 8
32M x 16
64M x 8
Max Freq.
B3(DDR333@CL=2.5)
B0(DDR266@CL=2.5)
B3(DDR333@CL=2.5)
B0(DDR266@CL=2.5)
B3(DDR333@CL=2.5)
B0(DDR266@CL=2.5)
B3(DDR333@CL=2.5)
B0(DDR266@CL=2.5)
Interface
SSTL2
SSTL2
SSTL2
SSTL2
Package
66pin TSOP II
66pin TSOP II
60 FBGA
60 FBGA
3.0 Operating Frequencies
B3(DDR333@CL=2.5)
Speed @CL2
Speed @CL2.5
Speed @CL3
CL-tRCD-tRP
133MHz
166MHz
-
2.5-3-3
B0(DDR266@CL=2.5)
100MHz
133MHz
-
2.5-3-3
Rev. 1.6 January 2006
K4H510838C
K4H511638C
Industrial
DDR SDRAM
16Mb x 16
32Mb x 8
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
WE
CAS
RAS
CS
NC
BA0
BA1
AP/A10
A0
A1
A2
A3
VDD
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
WE
CAS
RAS
CS
NC
BA0
BA1
AP/A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
4.0 Pin Description of TSOP
66Pin TSOPII
(400mil x 875mil)
(0.65mm Pin Pitch)
Bank Address
BA0~BA1
Auto Precharge
A10
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
512Mb TSOP-II Package Pinout
5.0 Ball Description of FBGA
16M x 16
1
2
3
7
8
9
VSSQ
DQ15
VSS
A
VDD
DQ0
VDDQ
DQ14
VDDQ
DQ13
B
DQ2
VSSQ
DQ1
DQ12
VSSQ
DQ11
C
DQ4
VDDQ
DQ3
DQ10
VDDQ
DQ9
D
DQ6
VSSQ
DQ5
DQ8
VSSQ
UDQS
E
LDQS
VDDQ
DQ7
VREF
VSS
UDM
F
LDM
VDD
NC
CK
CK
G
WE
CAS
A12
CKE
H
RAS
CS
A11
A9
J
BA1
BA0
A8
A7
K
A0
A10/AP
A6
A5
L
A2
A1
A4
VSS
M
VDD
A3
64M x 8
1
2
3
7
8
9
VSSQ
DQ7
VSS
A
VDD
DQ0
VDDQ
NC
VDDQ
DQ6
B
DQ1
VSSQ
NC
NC
VSSQ
DQ5
C
DQ2
VDDQ
NC
NC
VDDQ
DQ4
D
DQ3
VSSQ
NC
NC
VSSQ
DQS
E
NC
VDDQ
NC
VREF
VSS
DM
F
NC
VDD
NC
CK
CK
G
WE
CAS
A12
CKE
H
RAS
CS
A11
A9
J
BA1
BA0
A8
A7
K
A0
A10/AP
A6
A5
L
A2
A1
A4
VSS
M
VDD
A3
Organization
64Mx8
32Mx16
Row Address
A0~A12
A0~A12
Column Address
A0-A9, A11
A0-A9
DM is internally loaded to match DQ and DQS identically.
Row & Column address configuration
Rev. 1.6 January 2006
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