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71256TTSA12PZG

Description
Application Specific SRAM, 32KX8, 12ns, CMOS, PDSO28
Categorystorage    storage   
File Size80KB,8 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
Download Datasheet Parametric View All

71256TTSA12PZG Overview

Application Specific SRAM, 32KX8, 12ns, CMOS, PDSO28

71256TTSA12PZG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Objectid1126067486
Reach Compliance Codecompliant
ECCN codeEAR99
Maximum access time12 ns
I/O typeCOMMON
JESD-30 codeR-PDSO-G28
JESD-609 codee3
memory density262144 bit
Memory IC TypeAPPLICATION SPECIFIC SRAM
memory width8
Humidity sensitivity level3
Number of terminals28
word count32768 words
character code32000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP28,.53,22
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Parallel/SerialPARALLEL
power supply5 V
Certification statusNot Qualified
Maximum standby current0.015 A
Minimum standby current4.5 V
Maximum slew rate0.16 mA
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch0.55 mm
Terminal locationDUAL
CMOS Static RAM
256K (32K x 8-Bit)
Features
32K x 8 advanced high-speed CMOS static RAM
Commercial (0° to 70°C) and Industrial (-40° to 85°C)
temperature options
Equal access and cycle times
– Commercial and Industrial: 12/15/20/25ns
One Chip Select plus one Output Enable pin
Bidirectional data inputs and outputs directly
TTL-compatible
Low power consumption via chip deselect
Commercial product available in 28-pin 300- and 600-mil
Plastic DIP, 300 mil Plastic SOJ and TSOP packages
Industrial product available in 28-pin 300 mil Plastic SOJ
and TSOP packages
IDT71256SA/TTSA
Description
The IDT71256SA is a 262,144-bit high-speed Static RAM organized
as 32K x 8. It is fabricated using IDT’s high-perfomance, high-reliability
CMOS technology. This state-of-the-art technology, combined with
innovative circuit design techniques, provides a cost-effective solution for
high-speed memory needs.
The IDT71256SA has an output enable pin which operates as fast as
6ns, with address access times as fast as 12ns. All bidirectional inputs and
outputs of the IDT71256SA are TTL-compatible and operation is from a
single 5V supply. Fully static asynchronous circuitry is used, requiring no
clocks or refresh for operation.
The IDT71256SA is packaged in 28-pin 300- and 600-mil Plastic DIP,
28-pin 300 mil Plastic SOJ and TSOP.
Functional Block Diagram
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
ADDRESS
DECODER
262,144-BIT
MEMORY
ARRAY
,
I/O
0 -
I/O
7
8
8
I/O CONTROL
2948 drw 01
CS
WE
OE
CONTROL
LOGIC
FEBRUARY 2007
1
©2007 Integrated Device Technology, Inc.
DSC-2948/09
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