BU-63825F2-350K datasheet, PDF

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> BU-63825F2-350K

BU-63825F2-350K: DescriptionMil-Std-1553 Controller, 0.125MBps, CMOS, CQFP70, FLATPACK-70; CategoryThe embedded processor and controller Microcontrollers and processors; File Size257KB，4 Pages; ManufacturerData Device Corporation

Download Datasheet Parametric View All

BU-63825F2-350K Overview

Mil-Std-1553 Controller, 0.125MBps, CMOS, CQFP70, FLATPACK-70

BU-63825F2-350K Parametric

Parameter Name	Attribute value
Objectid	2008827066
package instruction	QFF,
Reach Compliance Code	compliant
Country Of Origin	Taiwan, USA
YTEOL	7.55
Other features	WD-MAX
Address bus width
boundary scan	NO
maximum clock frequency	16 MHz
letter of agreement	MIL-STD-1553
Data encoding/decoding methods	BIPH-LEVEL(MANCHESTER)
Maximum data transfer rate	0.125 MBps
External data bus width
JESD-30 code	R-CQFP-F70
length	48.26 mm
low power mode	YES
Number of serial I/Os	2
Number of terminals	70
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QFF
Package shape	RECTANGULAR
Package form	FLATPACK
Filter level	MIL-PRF-38534
Maximum seat height	5.46 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	QUAD
width	26 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, MIL-STD-1553

Preview

Download Datasheet

View All

www.ddc-web.com

MIL-STD-1553 Terminals for

Space Applications:

MODEL:BU-63825(925) and BU-63705

FEATURES:

BU-63705:

•

Drop-in Replacement for BU-61582 (83)

•

Drop-in Replacement for BU-65142

•

Rad Tolerant & Rad Hard Versions*

•

Rad Tolerant & Rad Hard Versions*

•

Fully Integrated Remote Terminal

•

Fully Integrated 1553 - BC/RT/MT

Including:

•

Flexible Processor Interface

- Low-Power Transceivers

•

16K x 16 Internal RAM

- Complete RT Protocol

•

Intelligent RT Data Buffering

•

Direct Interface to Processorless

•

Multiple Ordering Options;

Systems

+5V (Only), +5V/-15V, +5V/-12V

•

High Reliability Screening

+5V/Transceiverless (Contact Factory for

•

Multiple Ordering Options;

Availability)

+5V (Only), +5V/-15V, and +5V/-12V

+5V (Only, with Transmit Inhibits)

BU-63825(925):

DESCRIPTION

The BU-63825/925 BC/RT/MT Sp’ACE-II and BU-63705 Space-RT-II series of MIL-STD-1553 terminals continues Data

Device Corporation’s (DDC’s) commitment to producing hybrids with enhanced processing and screening for space

borne, radiation and Hi-Rel applications. Both terminals are designed specifically to be hardware and software

compatible, direct drop-in replacements for the equivalent Sp’ACE and Space RT series.

The BU-63825/925 Sp’ACE-II is a complete integrated interface between a 1553 bus and a host processor, and

replaces the BU-61582/83 Sp’ACE ( Space Advanced Communication Engine) pin-for-pin with the same 1.9 square

inch package.

The BU-63705 Space RT-II is a terminal for simple, non-CPU based applications, and shares the same 3.78 square inch

package as BU-65142 Space RT, which it replaces.

APPLICATIONS

The new generation of Sp’ACE-II and Space-RT-II terminals are designed for applications requiring the highest levels

of reliability and radiation tolerance*, including such platforms as launch vehicles, satellites and the International

Space Station.

DESIGN

The manufacturing of hybrids for space applications involves enhancements in the area of layout design, processing

and screening. The principle goal of the hybrid mechanical design is to improve the ease of wire bonding and

inspection. All of DDC's space grade terminals utilize ceramic packaging. Ceramic packages eliminate the potential

hermeticity problems associated with the glass beads of KOVAR (metal) packages. In addition, ceramic packages

facilitate improved thermal properties and feature reduced weight and lower cost.

*Contact Factory For Radiation Reports and Test Conditions

All trademarks are the property of their respective owners

Make Sure the Next Card

You Purchase Has...

Recommended Resources

Photoelectric control digital tube display circuit

Zero trigger thyristor temperature control circuit 4

One of the transistor-type water level automatic control circuits (fill-in type) a

Use fluorescent lamp starter to make household appliance indicator circuit

555 simple power adjustment circuit

Application wiring diagram of TX-KD301 (driver)

Detailed explanation of STM32 DFU file generation: Recently, it seems that many people are asking about the use of DFU files. We just studied it and would like to tell you how to use it. The first step is to prepare the files to be converted, in bmp a...; thinkz stm32/stm8

PLL settings for st7LITE05: I can't find the PLL selection byte in the ST7FLITE05.H header file of st7lite05. How can I solve this problem? How can I implement PLL to make the CPU work at 8MHz?...; xia_23 stm32/stm8

Ask for help from a master to assemble PIC12F: 12F629, I am a novice, I wrote a program to require GP0 to detect input, then GP1 output. START CLRF GPIO ; Initialize GPIO BCF STATUS, RP0 ; Select Bank0 MOVLW 07h ; Set GP to digital IO MOVWF CMCON ...; dtxiaozilong Microchip MCU

[FPGA learning series - AS and JTAG, sof and pof]: [align=left][size=6]Because FPGA is an SRAM structure, which is different from the ROM structure of CPLD, the FPGA code is lost after power failure, and an external configuration chip is required. Whe...; 白丁 FPGA/CPLD

【Play with C2000 Launchpad】Rookie LESSON9-Clock: Clock is an indispensable part of DSP and a necessary condition for its operation. Clock input: There are many clock options for the 280x series DSP, including: (1) Crystal input through X1 and X2: CL...; 常见泽1 Microcontroller MCU

IC design solutions for the future: [table][tr][td][align=center][size=16px]Future-oriented [url=http://www.szhexian.cn/][b][color=#599100]IC[/color][/b][/url] design solutions[/size][/align]With the rapid development of the integrated ...; cobble1 FPGA/CPLD

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components