TRI-STATE; ENABLE/DISABLE FUNCTION; DIFFERENTIAL OUTPUT; SELECTABLE O/P FREQUENCY
Frequency Adjustment - Mechanical
NO
frequency stability
50%
Installation features
SURFACE MOUNT
Number of terminals
14
Nominal operating frequency
100 MHz
Maximum operating temperature
70 °C
Minimum operating temperature
-20 °C
Oscillator type
LVPECL
Output load
50 OHM
Package body material
PLASTIC/EPOXY
Encapsulate equivalent code
LCC14,.1X.12,20
physical size
3.2mm X 2.5mm X 0.85 mm
Maximum slew rate
26 mA
Maximum supply voltage
3.6 V
Minimum supply voltage
2.25 V
surface mount
YES
maximum symmetry
52/48 %
DSC2022CE1-A0001T Preview
DSC2022
Low-Jitter Configurable Dual LVPECL Oscillator
General Description
The DSC2022 series of high performance
dual output oscillators utilizes a proven
silicon MEMS technology to provide excellent
jitter and stability while incorporating
additional device functionality.
The two
outputs are controlled by separate supply
voltages to allow for high output isolation.
The frequencies of the outputs can be
identical or independently derived from a
common PLL frequency source.
The
DSC2022 has provision for up to eight user-
defined
pre-programmed,
pin-selectable
output frequency combinations.
DSC2022 is packaged in a 14-pin 3.2x2.5
mm
QFN
package
and
available
in
temperature grades from Ext. Commercial to
Industrial.
Features
Low RMS Phase Jitter: <1 ps (typ)
High Stability: ±10, ±25, ±50 ppm
Wide Temperature Range
o
Industrial: -40° to 85° C
o
Ext. commercial: -20° to 70° C
High Supply Noise Rejection: -50 dBc
Two Independent LVPECL Outputs
Pin-Selectable Configurations
o
3-bit Output Frequency Combinations
Short Lead Times: 2 Weeks
Wide Frequency Range: 10 to 425
MHz
Miniature Footprint of 3.2x2.5mm
2
Excellent Shock & Vibration Immunity
o
Qualified to MIL-STD-883
High Reliability
o
20x better MTF than quartz oscillators
Supply Range of 2.25 to 3.6 V
Lead Free & RoHS Compliant
Block Diagram
Applications
Storage Area Networks
o
SATA, SAS, Fibre Channel
Passive Optical Networks
o
EPON, 10G-EPON, GPON, 10G-PON
Ethernet
o
1G, 10GBASE-T/KR/LR/SR, and FCoE
HD/SD/SDI Video & Surveillance
PCI Express
All Rights Reserved. No part of this document may be copied or reproduced in any form without the prior written permission of Discera, Inc. Discera Inc. may update or make
changes to the contents, products, programs or services described at any time without notice. This document neither states nor implies any kind of warranty, including, but not
limited to implied warranties of merchantability or fitness for a particular use.
Enables outputs when high and disables (tri-state) them when low
Leave unconnected or grounded
Leave unconnected or grounded
Ground
Least significant bit for frequency selection
Middle bit for frequency selection
Most significant bit for frequency selection
Positive LVPECL Output 1
Negative LVPECL Output 1
Negative LVPECL Output 2
Positive LVPECL Output 2
Power Supply 2 for LVPECL Output 2
Power Supply
Leave unconnected or grounded
General Description
The DSC2022 is a dual output LVPECL
oscillator consisting of a MEMS resonator and
a support PLL IC.
The two outputs are
generated
through
independent
8-bit
programmable dividers from the output of the
internal PLL. Two constraints are imposed on
the output frequencies: 1) f
2
=M x f
1
/N, where
M and N are even integers between 4 and
254, 2) 1.2GHz < N x f
2
< 1.7GHz.
The actual frequencies output by the DSC2022
are controlled by an internal pre-programmed
memory (OTP).
This memory stores all
coefficients required by the PLL for up to eight
different frequency combinations.
Three
control pins (FS0 – FS2) select the output
frequency combination.
Discera supports
customer defined versions of the DSC2022.
Standard frequency options are described in in
the following sections.
When Enable (pin 1) is floated or connected to
VDD, the DSC2022 is in operational mode.
Driving Enable to ground will tri-state both
output drivers (hi-impedance mode).
Output Frequency Combinations
Table 1 lists the standard frequency configurations and the associated ordering information to be
used in conjunction with the ordering code. Customer defined combinations are available.
Table 1. Pre-programmed pin-selectable output frequency combinations
Ordering
Info
A0001
A0002
Freq
(MHz)
f
OUT1
f
OUT2
f
OUT1
f
OUT2
Freq Select Bits [FS2, FS1, FS0] –
Default is [111]
000
106.25
75
001
100
100
010
125
125
011
156.25
156.25
100
156.25
25
101
156.25
125
110
125
25
111
400
200
Contact factory for additional configurations.
Frequency select bit are weakly tied high so if left unconnected the default setting will be [111] and
the device will output the associated frequency highlighted in
Bold.
All Rights Reserved. No part of this document may be copied or reproduced in any form without the prior written permission of Discera, Inc. Discera Inc. may update or make
changes to the contents, products, programs or services described at any time without notice. This document neither states nor implies any kind of warranty, including, but not
limited to implied warranties of merchantability or fitness for a particular use.
Note: 1000+ years of data retention on internal memory
Specifications
(Unless specified otherwise: T=25° C)
Parameter
Supply Voltage
1
Supply Current
Supply Current
2
Frequency Stability
Aging
Startup Time
3
Input Logic Levels
Input logic high
Input logic low
Output Disable Time
4
Output Enable Time
Pull-Up Resistor
2
Output Logic Levels
Output logic high
Output logic low
Pk to Pk Output Swing
Output Transition time
Rise Time
Fall Time
Frequency
Output Duty Cycle
Period Jitter
5
Integrated Phase Noise
Spurious Frequencies
6
Notes:
1.
2.
3.
4.
5.
6.
Pin 4 V
DD
should be filtered with 0.01uf capacitor.
Output is enabled if Enable pad is floated or not connected.
t
su
is time to stable output frequency after V
DD
is applied and outputs are enabled.
Output Waveform and Test Circuit figures below define the parameters.
Period Jitter includes crosstalk from adjacent output.
Spurious frequencies include crosstalk from adjacent output within 20 MHz of the output clock frequency.
4
Condition
V
DD
I
DD
I
DD
Δf
Δf
t
SU
V
IH
V
IL
t
DA
t
EN
Pull-up exists on all digital IO
EN pin low – outputs are disabled
EN pin high – outputs are enabled
LVPECL: R
L
=50Ω, F
0
=156.25 MHz
Includes frequency variations due
to initial tolerance, temp. and
power supply voltage
1 year @25°C
T=25°C
Min.
2.25
Typ.
21
89
Max.
3.6
26
Unit
V
mA
mA
±10
±25
±50
±5
10
0.75xV
DD
-
-
0.25xV
DD
100
5
33
ppm
ppm
ms
V
ns
us
kΩ
LVPECL Outputs
V
OH
V
OL
R
L
=50Ω
Single-Ended
t
R
t
F
f
0
SYM
J
PER
J
PH
20% to 80%
R
L
=50Ω, C
L
= 2pF
Single Frequency
Differential
F
01
= 156.25 MHz
F
02
= 156.25 MHz
200kHz to 20MHz @156.25MHz
100kHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
10
48
3.3
0.3
0.5
1.9
-50
V
DD
-1.08
-
830
250
425
52
-
V
DD
-1.55
V
mV
ps
MHz
%
ps
RMS
ps
RMS
dBc
3
All Rights Reserved. No part of this document may be copied or reproduced in any form without the prior written permission of Discera, Inc. Discera Inc. may update or make
changes to the contents, products, programs or services described at any time without notice. This document neither states nor implies any kind of warranty, including, but not
limited to implied warranties of merchantability or fitness for a particular use.
All Rights Reserved. No part of this document may be copied or reproduced in any form without the prior written permission of Discera, Inc. Discera Inc. may update or make
changes to the contents, products, programs or services described at any time without notice. This document neither states nor implies any kind of warranty, including, but not
limited to implied warranties of merchantability or fitness for a particular use.
All Rights Reserved. No part of this document may be copied or reproduced in any form without the prior written permission of Discera, Inc. Discera Inc. may update or make
changes to the contents, products, programs or services described at any time without notice. This document neither states nor implies any kind of warranty, including, but not
limited to implied warranties of merchantability or fitness for a particular use.
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