Vectron’s VC-806 Crystal Oscillator is a quartz stabilized, differential output oscillator, operating off either a 2.5 or 3.3 volt supply in a
hermetically sealed 3.2 x 5.0mm ceramic package.
Features
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Ultra Low Jitter Performance
Fundamental or 3rd OT Crystal Design
Output Frequencies to 250.000MHz
<0.7 ps RMS jitter, 12kHz-20MHz
Differential Output
Enable/Disable
-10/70°C, -40/85°C and -40/105°C Operating Temperature Range
Hermetically Sealed 3.2 x 5.0mm Ceramic Package
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Applications
Storage Area Networking
Telecom
Ethernet, GE, SynchE
Fiber Channel
PON
Driving A/D’s, D/A’s, FPGA’s
Test and Measurement
Medical
COTS
• Product is compliant to RoHS directive
and fully compatible with lead free assembly
Block Diagram
Complementary
Output
Output
V
DD
Crystal
Oscillator
E/D or NC
E/D or NC
Gnd
Page1
Performance Specifications
Table 1. Electrical Performance, LVPECL Option
Parameter
Supply Voltage
1
(Ordering Option)
Current (No Load)
Nominal Frequency
2
Stability
3
(Ordering Option)
Outputs
Output Logic Levels
4
, -10/70°C
Output Logic High
Output Logic Low
Output Logic Levels
4
, -40/105°C
Output Logic High
Output Logic Low
Output Rise and Fall Time
4
Load
Duty Cycle
5
Phase Jitter
6
, 156.25MHz
12kHz - 20MHz offset
Period Jitter
7
RMS
P/P
Random Jitter
Deterministic Jitter
Output Enabled
8
Output Disabled
Enable/Disable Time
Enable/Disable Leakage Current
Enable Pull-Up Resistor
Output Enabled
Output Disabled
Start-Up Time
Operating Temperature Range (Ordering Option)
9
Package Size
t
SU
T
OP
-10/70 or -40/85 or -40/105
3.2 x 5.0 x 1.3
33
1
10
фJ
фJ
2.6
23
2.6
<0.2
0.7*V
DD
0.3*V
DD
200
±200
ps
ps
ps
ps
V
V
ns
uA
KOhm
MOhm
ms
°C
mm
45
V
V
OH
V
OL
V
OH
V
OL
t
R
/ t
F
50 ohms into V
DD
-1.3V
50
0.3
55
0.7
%
ps
V
DD
-1.025
V
DD
-1.810
V
DD
-1.085
V
DD
-1.830
V
DD
-0.880
V
DD
-1.620
V
V
DD
-0.880
V
DD
-1.555
700
ps
Symbol
Supply
V
DD
I
DD
Frequency
f
N
Min
3.135
2.375
Typ
3.3
2.5
Max
3.465
2.625
75
Units
V
mA
MHz
ppm
25
±25, ±50, ±100
250
R
J
D
J
Enable/Disable
V
IH
V
IL
t
D
1.
The VC-806 power supply pin should be filtered, eg, a 0.1 and 0.01uf capacitor.
2. See Standard Frequencies and Ordering Information for more information.
3. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR reflow.
4. Figure 1 shows the test circuit and Figure 2 defines these parameters.
5. Duty Cycle is defines as the On/Time Period.
6. Measured using an Agilent E5052 Signal Source Analyzer at 25 °C. Phase Jitter will be 1.0ps (max) for carrier frequencies between 25MHz
and 100MHz. Above 100MHz carrier frequency, phase jitter will be 0.7ps (max).
7. Measured using a Wavecrest SIA3300C, 90K samples.
8. Outputs will be Enabled if Enable/Disable is left open.
9. Only ±50ppm and ±100ppm stability options are available for -40 °C to 105 °C operating temperature range.
Page2
Performance Specifications
Table 2. Electrical Performance, LVDS Option
Parameter
Supply Voltage
1
(Ordering Option)
Current (No Load)
Nominal Frequency
2
Stability
3
(Ordering Option)
Outputs
Output Logic Levels
4
Output Logic High
Output Logic Low
Output Swing
Differential Output Error
Offset Voltage
Offset Voltage Error
Output Leakage Current
Output Rise and Fall Time
4
Load
Duty Cycle
5
Phase Jitter
6
, 156.25MHz
12kHz - 20MHz offset
Period Jitter
7
RMS
P/P
Random Jitter
Deterministic Jitter
Output Enabled
8
Output Disabled
Enable/Disable Time
Enable/Disable Leakage Current
Enable Pull-Up Resistor
Output Enabled
Output Disabled
Start-Up Time
Operating Temperature Range (Ordering Option)
9
Package Size
t
SU
T
OP
-10/70 or -40/85 or -40/105
3.2 x 5.0 x 1.3
33
1
10
фJ
фJ
2.9
25.1
2.9
<0.2
0.7*V
DD
0.3*V
DD
200
±200
ps
ps
ps
ps
V
V
ns
uA
KOhm
MOhm
ms
°C
mm
45
t
R
/ t
F
100 ohms differential
50
0.35
55
0.8
%
ps
1.125
1.25
V
V
OH
V
OL
0.9
247
1.43
1.10
330
1.6
454
50
1.375
50
10
700
mV
mV
V
mV
uA
ps
Symbol
Supply
V
DD
I
DD
Frequency
f
N
Min
3.135
2.375
Typ
3.3
2.5
Max
3.465
2.625
60
Units
V
mA
MHz
ppm
25
±25, ±50, ±100
250
R
J
D
J
Enable/Disable
V
IH
V
IL
t
D
1.
The VC-806 power supply pin should be filtered, eg, a 0.1 and 0.01uf capacitor.
2. See Standard Frequencies and Ordering Information for more information.
3. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR reflow.
4. Figure 3 shows the test circuit and Figure 2 defines these parameters.
5. Duty Cycle is defines as the On/Time Period.
6. Measured using an Agilent E5052 Signal Source Analyzer at 25 °C. Phase Jitter will be 1.0ps (max) for carrier frequencies between 25MHz
and 100MHz. Above 100MHz carrier frequency, phase jitter will be 0.8ps (max).
7. Measured using a Wavecrest SIA3300C, 90K samples.
8. Outputs will be Enabled if Enable/Disable is left open.
9. Only ±50ppm and ±100ppm stability options are available for -40 °C to 105 °C operating temperature range.
Page3
Test Diagrams
t
R
0.8*V
amp
50%
Figure 1 - LV-PECL test circuit
t
F
0.2*V
amp
On Time
Period
Figure 2 - Waveform
Figure 3 - LVDS test circuit
Package and Pinout
Table 3. Pinout
Pin #
1
2
3
4
5
6
Symbol
E/D or NC
E/D or NC
GND
f
O
Cf
O
V
DD
Function
Enable Disable or No Connection
Enable Disable or No Connection
Electrical and Lid Ground
Output Frequency
Complementary Output Frequency
Supply Voltage
The Enable/Disable function is set at the factory on either pin 1 or pin
2 and is an ordering option.
Table 4. Enable Disable Function
E/D Pin
High
Open
Low
Output
Clock Output
Clock Output
High Impedance
Figure 4 - Package (Dimensions in mm)
0.38
Marking Information:
V: Vectron
XXMXXX: Frequency in MHz (Example: 25M000 or 125M00)
YYWW: Year and Week (1642: Year 2016 and Week 42)
Z: Manufacturing Location
Figure 5 - Pad Layout (Dimensions in mm)
Page4
LVPECL Application Diagrams
Figure 6 - Standard PECL
Output Configuration
Figure 7 - Single Resistor Termination Scheme
Resistor values are typically 140 ohms for
3.3V operation. Resistor values are typically
84 for 2.5V operation.
Figure 8 - Pull-Up Pull Down Termination
Resistor values are typically for 3.3V operation
For 2.5V operation, the resistor to ground is 62
ohms and the resistor to supply is 240 ohms
The VC-806 incorporates a standard PECL output scheme, which are un-terminated emitters as shown in Figure 6. There are numerous application notes
on terminating and interfacing PECL logic and the two most common methods are a single resistor to ground, Figure 7, and a pull-up/pull-down scheme
as shown in Figure 8. An AC coupling capacitor is optional, depending on the application and the input logic requirements of the next stage.
LVDS Application Diagrams
Figure 9 - Standard LVDS
Output Configuration
Figure 10 - LVDS to LVDS Connection, Internal 100ohm
Figure 11 - LVDS to LVDS Connection
Some LVDS structures have an internal 100 ohm resistor
External 100ohm and AC blocking caps
on the input and do not need additional components.
Some input structures may not have an internal 100 ohm
resistor on the input and will need an external 100ohm
resistor for impedance matching. Also, the input may have
an internal DC bias which may not be compatible with
LVDS levels, AC blocking capacitors can be used.
One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-termi-
nated, and if it one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching
into account. Load matching and power supply noise are the main contributors to jitter related problems.
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