K8A2815ET(B)M
FLASH MEMORY
Document Title
128M Bit (8M x16) Synchronous Burst , Multi Bank NOR Flash Memory
Revision History
Revision No. History
0.0
0.1
Preliminary
Revised
- Change the "Programmable Wait State" settings in Burst Mode
Configuration Register.(Refer to Table 7.)
- Change the max. Vcc from 1.9V to 1.95V
- Change the part number from K8S28158 to K8S2815E because of
Vcc change.
Revised
- Change the temperature range from Extended Temperature(-25°C ~
85°C) to Industrial Temperature(-40°C ~ 85°C)
- Add the Bottom Boot Block Address Table(Refer to Table 3-2)
- Change the max. of Vpp from 12.5V to 9.5V
Draft Date
June 28, 2002
September 4, 2002
Remark
0.2
September 25, 2002
0.3
Revised
November 2, 2002
- Change the max. value of "Output Enable to RDY Valid" from 20ns to
the value of t
BA
(Name is changed from t
OE
to t
OER
)
- Add the function of block protect/unprotect in Erase Suspend Mode
- Remove the AC parameter "t
CEH
"(CE hold time from CLK)
November 19, 2002
Revised
- Add the AC parameter t
WEA
(WE Disable to AVD Enable) in command
sequences timing
Revised
- Add the CLK parameters in AC parameter table
- Add the t
RDYA
in AC parameter table
- Add the Accerelated Chip Erase Time in Erase/Program
Performance table
- Release the t
RP
from 100ns to 200ns
- Change the default value of "RDY Active" in Burst Mode Configura-
tion Set
December 17, 2002
0.4
0.5
0.6
Revised
March 11, 2003
- Change the description of Asynchronous Random Access Time from
"70ns" to "88.5ns(54MHz)/70ns(66MHz)"
- Change the max. of standby current from 25uA to 30uA
Revised
- Change the word boundary size from 64 words to 16 words
- Change the Write Timing (Address latch point : from "AVD rising
edge" to "WE falling edge")
- Remove the "Die revision Information" access in Autoselect Mode
April 23, 2003
0.7
0.8
Revised
Nov 14, 2003
- Change the description of Asynchronous Random Access Time from
"88.5ns(54MHz)" to "90ns(54MHz)"
- Change the typ. of standby current from 5uA to 10uA
- Change the max. of standby current from 30uA to 50uA
1
Revision 1.0
September, 2004
K8A2815ET(B)M
FLASH MEMORY
128M Bit (8M x16) Synchronous Burst , Multi Bank NOR Flash Memory
FEATURES
•
Single Voltage, 1.7V to 1.95V for Read and Write operations
•
Organization
- 8,388,608 x 16 bit ( Word Mode Only)
•
Read While Program/Erase Operation
•
Multiple Bank Architecture
- 16 Banks (8Mb Partition)
•
Read Access Time (@ C
L
=30pF)
- Asynchronous Random Access Time :
90ns (54MHz) / 70ns (66MHz)
- Synchronous Random Access Time :
90ns (54MHz) / 71ns (66MHz)
- Burst Access Time :
14.5ns (54MHz) / 11ns (66MHz)
•
Burst Length :
- Continuous Linear Burst
- Linear Burst : 8-word & 16-word with No-wrap & Wrap
•
Block Architecture
- Eight 4Kword blocks and two hundreds fifty-five 32Kword
blocks
- Bank 0 contains eight 4 Kword blocks and fifteen 32Kword
blocks
- Bank 1 ~ Bank 15 contain two hundred forty 32Kword blocks
•
Reduce program time using the V
PP
•
Power Consumption (Typical value, C
L
=30pF)
- Burst Access Current : 25mA
- Program/Erase Current : 15mA
- Read While Program/Erase Current : 35mA
- Standby Mode/Auto Sleep Mode : 10uA
•
Block Protection/Unprotection
- Using the software command sequence
- Last two boot blocks are protected by WP=V
IL
- All blocks are protected by V
PP
=V
IL
•
Handshaking Feature
- Provides host system with minimum latency by monitoring
RDY
•
Erase Suspend/Resume
•
Program Suspend/Resume
•
Unlock Bypass Program/Erase
•
Hardware Reset (RESET)
•
Data Polling and Toggle Bits
- Provides a software method of detecting the status of program
or erase completion
•
Endurance
100K Program/Erase Cycles Minimum
•
Data Retention : 10 years
•
Industrial Temperature : -40°C ~ 85°C
•
Support Common Flash Memory Interface
•
Low Vcc Write Inhibit
•
Package : 64 - ball TBGA Type , 9x9mm
0.8 mm ball pitch
1.0mm (Max.) Thickness
GENERAL DESCRIPTION
The K8A2815E featuring single 1.8V power supply is a 128Mbit
Synchronous Burst Multi Bank Flash Memory organized as
8Mx16. The memory architecture of the device is designed to
divide its memory arrays into 263 blocks with independent hard-
ware protection. This block architecture provides highly flexible
erase and program capability. The K8A2815E NOR Flash con-
sists of sixteen banks. This device is capable of reading data
from one bank while programming or erasing in the other bank.
Regarding read access time, at 54MHz, the K8A2815E pro-
vides a burst access of 14.5ns with initial access times of 90ns
at 30pF. At 66MHz, the K8A2815E provides a burst access of
11ns with initial access times of 71ns at 30pF. The device per-
forms a program operation in units of 16 bits (Word) and erases
in units of a block. Single or multiple blocks can be erased. The
block erase operation is completed within typically 0.7 sec. The
device requires 15mA as program/erase current in the
extended temperature ranges.
The K8A2815E NOR Flash Memory is created by using Sam-
sung's advanced CMOS process technology.
PIN DESCRIPTION
Pin Name
A0 - A22
DQ0 - DQ15
CE
OE
RESET
V
PP
WE
WP
CLK
RDY
AVD
Vcc
V
SS
Pin Function
Address Inputs
Data input/output
Chip Enable
Output Enable
Hardware Reset Pin
Accelerates Programming
Write Enable
Hardware Write Protection Input
Clock
Ready Output
Address Valid Input
Power Supply
Ground
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
3
Revision 1.0
September, 2004
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