TC55V400AFT-55,-70
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
262,144-WORD BY 16-BIT FULL CMOS STATIC RAM
DESCRIPTION
The TC55V400AFT is a 4,194,304-bit static random access memory (SRAM) organized as 262,144 words by 16
bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to 3.6
V power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3
mA/MHz and a minimum cycle time of 55 ns. It is automatically placed in low-power mode at 0.5
mA
standby
current (at V
DD
=
3 V, Ta
=
25°C, maximum) when chip enable (
CE1
) is asserted high or (CE2) is asserted low.
There are three control inputs.
CE1
and CE2 are used to select the device and for data retention control, and
output enable (
OE
) provides fast memory access. Data byte control pin (
LB
,
UB
) provides lower and upper byte
access. This device is well suited to various microprocessor system applications where high speed, low power and
battery backup are required. And, with a guaranteed operating extreme temperature range of
-40°
to 85°C, the
TC55V400AFT can be used in environments exhibiting extreme temperature conditions. The TC55V400AFT is
available in normal and reverse pinout plastic 48-pin thin-small-outline package (TSOP).
FEATURES
·
·
·
·
·
·
·
Low-power dissipation
Operating: 10.8 mW/MHz (typical)
Single power supply voltage of 2.3 to 3.6 V
Power down features using
CE1
and CE2
Data retention supply voltage of 1.5 to 3.6 V
Direct TTL compatibility for all inputs and outputs
Wide operating temperature range of
-40°
to 85°C
Standby Current (maximum):
3.6 V
3.0 V
7
mA
5
mA
·
Access Times (maximum):
TC55V400AFT
-55
Access Time
CE1
Access Time
-70
70 ns
70 ns
70 ns
35 ns
55 ns
55 ns
55 ns
30 ns
CE2 Access Time
OE
Access Time
·
Package:
TSOPⅠ48-P-1214-0.50 (AFT) (Weight: 0.38 g typ)
PIN ASSIGNMENT
(TOP VIEW)
48 PIN TSOP
PIN NAMES
A0~A17
1
48
CE1
, CE2
Address Inputs
Chip Enable
Read/Write Control
Output Enable
Data Byte Control
Data Inputs/Outputs
Power
Ground
No Connection
R/W
OE
LB
,
UB
I/O1~I/O16
24
(Normal)
25
V
DD
GND
NC
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
1
A15
17
A17
33
I/O3
2
A14
18
A7
34
I/O11
3
A13
19
A6
35
I/O4
4
A12
20
A5
36
I/O12
5
A11
21
A4
37
V
DD
6
A10
22
A3
38
I/O5
7
A9
23
A2
39
8
A8
24
A1
40
9
NC
25
A0
41
10
NC
26
CE1
11
R/W
27
GND
43
12
CE2
28
OE
13
NC
29
I/O1
45
14
UB
15
LB
16
NC
32
I/O10
48
A16
30
I/O9
46
31
I/O2
47
NC
42
44
I/O13 I/O6
I/O14 I/O7
I/O15 I/O8
I/O16 GND
2001-09-04
1/11
TC55V400AFT-55,-70
BLOCK DIAGRAM
CE
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A17
ROW ADDRESS
BUFFER
ROW ADDRESS
REGISTER
ROW ADDRESS
DECODER
MEMORY CELL ARRAY
2,048
´
128
´
16
(4,194,304)
V
DD
GND
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O16
SENSE AMP
DATA
OUTPUT
BUFFER
CE
A0 A1 A2 A3 A14 A15 A16
DATA
INPUT
BUFFER
COLUMN ADDRESS
DECODER
COLUMN ADDERSS
REGISTER
COLUMN ADDRESS
BUFFER
CLOCK
GENERATOR
R/W
OE
UB
LB
CE1
CE
CE2
OPERATING MODE
MODE
Read
CE1
CE2
H
OE
R/W
H
LB
UB
I/O1~I/O8
Output
High-Z
Output
Input
High-Z
Input
High-Z
High-Z
DATA
OUTPUT
BUFFER
I/O9~I/O16
Output
Output
High-Z
Input
Input
High-Z
High-Z
High-Z
DATA
INPUT
BUFFER
POWER
I
DDO
I
DDO
I
DDO
I
DDO
I
DDO
I
DDO
I
DDO
I
DDS
L
L
L
H
L
L
Write
L
L
L
H
*
H
H
H
*
L
*
H
*
*
*
L
H
*
*
*
H
L
Output Deselect
Standby
*
= don't care
H = logic high
L = logic low
*
H
*
*
L
L
H
L
L
H
*
H
*
*
2001-09-04
2/11
TC55V400AFT-55,-70
MAXIMUM RATINGS
SYMBOL
V
DD
V
IN
V
I/O
P
D
T
solder
T
stg
T
opr
Power Supply Voltage
Input Voltage
Input/Output Voltage
Power Dissipation
Soldering Temperature (10s)
Storage Temperature
Operating Temperature
RATING
VALUE
-0.3~4.6
-0.3*~4.6
-0.5~V
DD
+
0.5
0.6
260
-55~150
-40~85
UNIT
V
V
V
W
°C
°C
°C
*:
-3.0
V when measured at a pulse width of 50ns
DC RECOMMENDED OPERATING CONDITIONS (
Ta
= -
40° to 85°C
)
SYMBOL
V
DD
V
IH
V
IL
V
DH
*:
PARAMETER
MIN
Power Supply Voltage
Input High Voltage
Input Low Voltage
Data Retention Supply Voltage
-3.0
V when measured at a pulse width of 50 ns
2.3
2.2
-0.3*
1.5
2.3 V~3.6 V
TYP
3.0
¾
¾
¾
MAX
3.6
V
DD
+
0.3
V
DD
´
0.22
3.6
V
V
V
V
UNIT
DC CHARACTERISTICS
(Ta
= -
40° to 85°C, V
DD
=
2.3 to 3.6 V)
SYMBOL
I
IL
I
OH
I
OL
I
LO
PARAMETER
Input Leakage
Current
Output High Current
Output Low Current
Output Leakage
Current
V
IN
=
0 V~V
DD
V
OH
=
V
DD
-
0.5 V
V
OL
=
0.4 V
CE1
=
V
IH
or CE2
=
V
IL
or R/W
=
V
IL
or
OE
=
V
IH
,
V
OUT
=
0 V~V
DD
CE1
=
V
IL
and CE2
=
V
IH
and
R/W
=
V
IH
and I
OUT
=
0 mA,
Other Input
=
V
IH
/V
IL
TEST CONDITION
MIN
¾
-0.5
2.1
¾
55 ns
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
TYP
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
0.05
¾
¾
MAX
±1.0
¾
¾
±1.0
70
60
10
65
55
5
2
0.6
6
0.7
7
0.5
1
5
UNIT
mA
mA
mA
mA
l
DDO1
Operating Current
l
DDO2
V
DD
=
t
3 V
±
10%
cycle
70 ns
1
ms
55 ns
70 ns
1
ms
mA
CE1
=
0.2 V and
V
DD
=
CE2
=
V
DD
-
0.2 V and
t
R/W
=
V
DD
-
0.2 V, I
OUT
=
0 mA, 3 V
±
10%
cycle
Other Input
=
V
DD
-
0.2 V/0.2 V
CE
=
V
IH
or CE2
=
V
IL
mA
I
DDS1
mA
V
DD
=
3 V
±
10%
I
DDS2
(Note)
Standby Current
CE1
=
V
DD
-
0.2 V
or CE2
=
0.2 V
V
DD
=
1.5 V~3.6 V
Ta
=
25°C
Ta
= -40~85°C
Ta
=
25°C
Ta
= -40~85°C
Ta
=
25°C
Ta
= -40~40°C
Ta
= -40~85°C
V
DD
=
3.3 V
±
0.3 V
V
DD
=
3.0 V
mA
Note:
In standby mode with
CE1
³
V
DD
-
0.2 V, these limits are assured for the condition CE2
³
V
DD
-
0.2 V or CE2
£
0.2 V.
CAPACITANCE
(Ta
=
25°C, f
=
1 MHz)
SYMBOL
C
IN
C
OUT
Note:
PARAMETER
Input Capacitance
Output Capacitance
V
IN
=
GND
V
OUT
=
GND
TEST CONDITION
MAX
10
10
UNIT
pF
pF
This parameter is periodically sampled and is not 100% tested.
2001-09-04
3/11
TC55V400AFT-55,-70
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta
= -
40° to 85°C, V
DD
=
2.7 to 3.6 V)
READ CYCLE
TC55V400AFT
SYMBOL
PARAMETER
MIN
t
RC
t
ACC
t
CO1
t
CO2
t
OE
t
BA
t
COE
t
OEE
t
BE
t
OD
t
ODO
t
BD
t
OH
Read Cycle Time
Address Access Time
Chip Enable(
CE1
) Access Time
Chip Enable(CE2) Access Time
Output Enable Access Time
Data Byte Control Access Time
Chip Enable Low to Output Active
Output Enable Low to Output Active
Data Byte Control Low to Output Active
Chip Enable High to Output High-Z
Output Enable High to Output High-Z
Data Byte Control High to Output High-Z
Output Data Hold Time
55
¾
¾
¾
¾
¾
5
0
0
¾
¾
¾
10
-55
MAX
¾
55
55
55
30
30
¾
¾
¾
25
25
25
¾
MIN
70
¾
¾
¾
¾
¾
5
0
0
¾
¾
¾
10
-70
MAX
¾
70
70
70
35
35
¾
¾
¾
30
30
30
¾
ns
UNIT
WRITE CYCLE
TC55V400AFT
SYMBOL
PARAMETER
MIN
t
WC
t
WP
t
CW
t
BW
t
AS
t
WR
t
ODW
t
OEW
t
DS
t
DH
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Byte Control to End of Write
Address Setup Time
Write Recovery Time
R/W Low to Output High-Z
R/W High to Output Active
Data Setup Time
Data Hold Time
55
45
50
45
0
0
¾
0
25
0
-55
MAX
¾
¾
¾
¾
¾
¾
25
¾
¾
¾
MIN
70
50
60
50
0
0
¾
0
30
0
-70
MAX
¾
¾
¾
¾
¾
¾
30
¾
¾
¾
ns
UNIT
AC TEST CONDITIONS
PARAMETER
Output load
Input pulse level
Timing measurements
Reference level
t
R
, t
F
TEST CONDITION
30 pF
+
1 TTL Gate
0.4 V, 2.4 V
V
DD
´
0.5
V
DD
´
0.5
5 ns
2001-09-04
4/11
TC55V400AFT-55,-70
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta
= -
40° to 85°C, V
DD
=
2.3 to 3.6 V)
READ CYCLE
TC55V400AFT
SYMBOL
PARAMETER
MIN
t
RC
t
ACC
t
CO1
t
CO2
t
OE
t
BA
t
COE
t
OEE
t
BE
t
OD
t
ODO
t
BD
t
OH
Read Cycle Time
Address Access Time
Chip Enable(
CE1
) Access Time
Chip Enable(CE2) Access Time
Output Enable Access Time
Data Byte Control Access Time
Chip Enable Low to Output Active
Output Enable Low to Output Active
Data Byte Control Low to Output Active
Chip Enable High to Output High-Z
Output Enable High to Output High-Z
Data Byte Control High to Output High-Z
Output Data Hold Time
70
¾
¾
¾
¾
¾
5
0
0
¾
¾
¾
10
-55
MAX
¾
70
70
70
35
35
¾
¾
¾
30
30
30
¾
MIN
85
¾
¾
¾
¾
¾
5
0
0
¾
¾
¾
10
-70
MAX
¾
85
85
85
45
45
¾
¾
¾
35
35
35
¾
ns
UNIT
WRITE CYCLE
TC55V400AFT
SYMBOL
PARAMETER
MIN
t
WC
t
WP
t
CW
t
BW
t
AS
t
WR
t
ODW
t
OEW
t
DS
t
DH
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Byte Control to End of Write
Address Setup Time
Write Recovery Time
R/W Low to Output High-Z
R/W High to Output Active
Data Setup Time
Data Hold Time
70
50
60
50
0
0
¾
0
30
0
-55
MAX
¾
¾
¾
¾
¾
¾
30
¾
¾
¾
MIN
85
55
70
55
0
0
¾
0
35
0
-70
MAX
¾
¾
¾
¾
¾
¾
35
¾
¾
¾
ns
UNIT
AC TEST CONDITIONS
PARAMETER
Output load
Input pulse level
Timing measurements
Reference level
t
R
, t
F
TEST CONDITION
30 pF
+
1 TTL Gate
V
DD
-
0.2 V, 0.2 V
V
DD
´
0.5
V
DD
´
0.5
5 ns
2001-09-04
5/11
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