PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843031
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
F
EATURES
•
1 differential 3.3V LVPECL output
•
Crystal oscillator interface designed for
18pF parallel resonant crystals
•
VCO frequency range: 580MHz - 700MHz
•
RMS phase jitter @312.5MHz (1.875MHz - 20MHz):
0.5ps (typical)
•
3.3V operating supply
•
0°C to 70°C ambient operating temperature
•
Industrial temperature information available upon request
G
ENERAL
D
ESCRIPTION
The ICS843031 is a 1 Gigabit Ethernet Clock
Generator and a member of the HiPerClocks
TM
HiPerClockS™
family of high performance devices from ICS. The
ICS843031 can synthesize 1 Gigabit Ethernet,
SONET, or Serial ATA reference clock frequencies
with the appropriate choice of crystal and output divider. The
ICS843031 has excellent phase jitter performance and is
packaged in a small 8-pin TSSOP, making it ideal for use in
systems with limited board space.
ICS
F
REQUENCY
T
ABLE
Inputs
Crystal Frequency (MHz)
25.92
26.04166
26.5625
M/N Ratio (Multiplier)
12
12
12
Output Frequency
(MHz)
311.04
312.5
318.75
B
LOCK
D
IAGRAM
OE
P
IN
A
SSIGNMENT
V
CC
XTAL_OUT
XTAL_IN
V
EE
1
2
3
4
8
7
6
5
Q0
nQ0
V
CC
OE
XTAL_IN
OSC
XTAL-OUT
Phase
Detector
VCO
÷2
nQ0
Q0
ICS843031
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
÷24
(fixed)
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
843031AG
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2004
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843031
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
Type
Power
Input
Power
Input
Pullup
Description
Core supply pin.
Cr ystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
Negative supply pin.
Output enable pin. LVCMOS/LVTTL interface levels.
Differential clock outputs. LVPECL interface levels.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 6
2, 3
4
5
7, 8
Name
V
CC
XTAL_OUT,
XTAL_IN
V
EE
OE
nQ0, Q0
Output
NOTE:
Pullup
refers to internal input resistors. See Table 2, Pin Characterristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
KΩ
843031AG
www.icst.com/products/hiperclocks.html
2
REV. A NOVEMBER 29, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843031
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
101.7°C/W (0 mps)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
=0°C
TO
70°C
Symbol
V
CC
I
EE
Parameter
Core Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
65
Maximum
3.465
Units
V
mA
T
ABLE
3B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
=0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
OE
OE
OE
OE
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
5
Units
V
V
µA
µA
T
ABLE
3C. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
=0°C
TO
70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
- 1.4
V
CC
- 2.0
0.6
Typical
Maximum
V
CC
- 0.9
V
CC
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
12
Test Conditions
Minimum
Typical
Fundamental
40
50
7
MHz
Ω
pF
Maximum
Units
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
=0°C
TO
70°C
Symbol
f
OUT
Parameter
Output Frequency
RMS Phase Jitter (Random);
NOTE 1
Output Rise/Fall Time
Test Conditions
Integration Range:
1.875MHz to 20MHz
20% to 80%
Minimum
Typical
312.5
0.5
550
50
Maximum
Units
MHz
ps
ps
%
REV. A NOVEMBER 29, 2004
t
jit(Ø)
t
R
/ t
F
odc
Output Duty Cycle
NOTE 1: Please refer to the Phase Noise Plot.
843031AG
www.icst.com/products/hiperclocks.html
3
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843031
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
T
YPICAL
P
HASE
N
OISE AT
312.5MH
Z
0
-10
-20
-30
-40
-50
-60
-70
➤
1 Gigabit Ethernet Filter
312.5MHz
RMS Phase Jitter (Random)
1.875Mhz to 20MHz = 0.50ps (typical)
N
OISE
P
OWER
dBc
Hz
-80
-90
-100
Raw Phase Noise Data
➤
-110
-120
-130
-140
-150
-160
-170
-180
-190
10
100
1k
➤
Phase Noise Result by adding 1
Gigabit Ethernet Filter to raw data
10k
100k
1M
10M
100M
O
FFSET
F
REQUENCY
(H
Z
)
843031AG
www.icst.com/products/hiperclocks.html
4
REV. A NOVEMBER 29, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843031
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
P
ARAMETER
M
EASUREMENT
I
NFORMATION
2V
Phase Noise Plot
LVPECL
nQx
V
EE
f
1
Offset Frequency
f
2
-1.3V ± 0.165V
RMS Jitter = Area Under Offset Frequency Markers
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
RMS P
HASE
J
ITTER
nQ0
Q0
Pulse Width
t
PERIOD
Noise Power
V
CC
Qx
SCOPE
80%
Clock
Outputs
80%
V
SW I N G
20%
t
R
t
F
20%
odc =
t
PW
t
PERIOD
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
843031AG
www.icst.com/products/hiperclocks.html
5
REV. A NOVEMBER 29, 2004
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