EEWORLDEEWORLDEEWORLD

Part Number

Search

Q19.9990-JXS21P4-8-10/50-AEC-HMR

Description
Parallel - Fundamental Quartz Crystal, 19.999MHz Nom, SMD, 4 PIN
CategoryPassive components    Crystal/resonator   
File Size2MB,2 Pages
ManufacturerJauch
Websitehttp://www.jauchusa.com/
Environmental Compliance
Download Datasheet Parametric View All

Q19.9990-JXS21P4-8-10/50-AEC-HMR Overview

Parallel - Fundamental Quartz Crystal, 19.999MHz Nom, SMD, 4 PIN

Q19.9990-JXS21P4-8-10/50-AEC-HMR Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Objectid145071167569
package instructionSMD, 4 PIN
Reach Compliance Codecompliant
Country Of OriginTaiwan
YTEOL7.25
Other featuresAEC-Q200; AT-CUT
Ageing1 PPM/FIRST YEAR
Crystal/Resonator TypePARALLEL - FUNDAMENTAL
Drive level10 µW
frequency stability0.005%
frequency tolerance10 ppm
JESD-609 codee4
load capacitance8 pF
Installation featuresSURFACE MOUNT
Nominal operating frequency19.999 MHz
Maximum operating temperature70 °C
Minimum operating temperature-20 °C
physical size2.0mm X 1.6mm X 0.55mm
Series resistance120 Ω
surface mountYES
Terminal surfaceNickel/Gold (Ni/Au)
Automotive SMD Crystal · JXS21P4
- 4 Pad Version, 2.0 x 1.6 mm
- seam sealed ceramic/metal package
- all versions are AEC-Q200 qualified
- HMR version with extended shock & vibration immunity
actual size
2011/65/EC
RoHS
RoHS compliant
Pb free
REACH
compliant
Conflict
mineral free
GENERAL DATA
TYPE
frequency range
frequency tolerance at 25 °C
load capacitance C
L
shunt capacitance C
O
storage temperature
shock resistance
drive level max.
aging
JXS21P4
16.0 ~ 40.0 MHz
(fund. AT-cut)
ESR (SERIES RESISTANCE RS)
frequency
in MHz
16.0 ~ 19.999
20.0 ~ 29.999
30.0 ~ 35.999
36.0 ~ 40.000
vibration
mode
fund. - AT
fund. - AT
fund. - AT
fund. - AT
ESR max.
in ½
150
100
80
60
ESR typ.
in ½
120
70
50
40
±10 ppm, ±20 ppm, ±30 ppm
8 pF / 10 pF / 12 pF standard
(option: 6 pF ~ 16 pF / series)
< 5 pF
-40 °C ~ +125 °C (T2, T3) / -40 °C ~ +85 °C (T1)
> 100 g
100 µW
(half sine pulse, 6.0 ms)*
(10 µW recommended)
< ±3 ppm first year (< ± 1 ppm for tol. ±10 ppm)
MARKING
* optional HMR version: 3000G / half sine pulse / 0.3 ms
TABLE 1: FREQUENCY STABILITY VS. TEMPERATURE
±15
ppm
±20
ppm
±25
ppm
frequency with load capacitance code
company code / date code / internal code
±50
ppm
±100
ppm
±30
ppm
date code: year/month; A ~ M: Jan. - Dec.; example 9A = 2019 January
9: 2019
0: 2020
1: 2021
2: 2022
3: 2023
4: 2024
Jan.
A
July
G
Febr.
B
Aug.
H
Mar.
C
Sept.
J
Apr.
D
Oct.
K
May
E
Nov.
L
June
F
Dec.
M
-20 °C ~ +70 °C
-40 °C ~ +85 °C
-40 °C ~ +105 °C
-40 °C ~ +125 °C
T1
T2
T3
available ∆ ask if available
DIMENSIONS
2.0
±0.1
#4
#3
1.6
±0.1
0.55 max.
#3
0.47
±0.05
0.64
±0.05
#4
#4
#3
1.1
±0.1
0.8
±0.1
1.4
±0.1
0.9
±0.1
0.50
±0.05
#1
#2
#2
#1
#1
#2
0.60
±0.05
top view
ORDER INFORMATION
side view
bottom view
#2–#4: connected to lid,
preferably connect to GND
crystal connection
pad layout
in mm
Q
Quartz
frequency
16.0 ~ 40.0 MHz
type
JXS21P4
load capacitance
8/10/12 pF std.
6 pF ~ 16 pF
S for series
tolerance at
25 °C
10 = ±10 ppm
20 = ±20 ppm
30 = ±30 ppm
stability vs.
temp. range
see table 1
blank =
T1 =
T2 =
T3 =
FU =
option 1
option 2
AEC = AEC-Q200 qualified
-20 °C ~ +70 °C
HMR = high mechanical reliability
-40 °C ~ +85 °C
(3000g/half sine wave/0.3ms)
-40 °C ~+105 °C
-40 °C ~+125 °C
for fundamental
frequencies ≥ 20 MHz
Example: Q 26.0-JXS21P4-12-30/50-T2-FU-AEC-LF
(Suffix LF = RoHS compliant / Pb free)
21032019
Jauch Quartz GmbH • e-mail: info@jauch.de • full data can bedata can be found under:
info@jauch.com
full found under: www.jauch.com
All specifications are subject to change without notice
www.jauch.de | www.jauch.co.uk | www.jauch.fr | www.jauchusa.com
About 28377d dual-core simulation and CLA simulation experience
Since 28377D has two CPUs and two CLAs, simulation is more troublesome. Record the operations during simulation. When simulating CPU2, because CPU2 is started by CPU1, CPU1 needs to set CPU2 startup M...
Aguilera Microcontroller MCU
DDR3 reference clock issues
[color=#000000]Use DDR3 SDRAM Controller with UniPHY to control DDR3, and the FPGA is stratix IV EP4SGX series[/color] [color=#000]1.Memory clock frequency 520MHz 2.Set[/color][font=Calibri][color=#00...
xiaoganer FPGA/CPLD
Vivado implementation error, please help
I am working on an IP core, and when I implement it, it keeps reporting "XXX is not placed", as shown in the picture:Is this a common problem? Please give me some advice:congratulate:...
zrqldg FPGA/CPLD
Help: Card reader system design based on FPGA
[i=s]This post was last edited by paulhyde on 2014-9-15 09:51[/i] :'( Please help me! I need to use DE2, but I can't find much information. If anyone has experience, please help me. Thank you!...
LLLY___111 Electronics Design Contest
The National Undergraduate Electronic Design Competition has been renamed
[i=s]This post was last edited by paulhyde on 2014-9-15 09:38[/i] [b]The National Undergraduate Electronic Design Competition has been officially named the NEC Electronics Cup National Undergraduate E...
roronoazoro Electronics Design Contest
High speed, high output current, voltage feedback amplifier MS8241, can replace LM7171, P=P
Product FeaturesMS8241is a high-speed voltage feedback amplifier with the high-speed conversion characteristics of a current feedback amplifier, and can be used in all traditional voltage feedback op ...
18025319604 Analogue and Mixed Signal

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2711  1244  1549  1459  17  55  26  32  30  1 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号