CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Temperature (T
A
) . . . . . . . . . . . . . . . . . . -40
o
C to +105
o
C
DC Operating Voltage Range (V
DD
) . . . . . . . . . . . . . . . . +4V to +7V
DC Electrical Specifications
PARAMETERS
SIGNAL I/O SECTION
Output Voltage High Level
Output Voltage Low Level
Input Voltage Low Level
Input Voltage High Level
Output High Drive (Source) Current
(REC Pin)
Output High Drive (Source) Current
(IDLE, Control Pins)
Output Low Drive (Sink) Current
(IDLE, Control, REC)
T
A
= -40
o
C to +105
o
C Unless Otherwise Noted. External Bias (V
O
) shall be 1.8V to 3.13V Unless
Otherwise Noted.
SYMBOLS
TEST CONDITIONS
MIN
MAX
UNITS
V
OL
V
OH
V
IL
V
IH
I
OH
I
OH
I
OL
Open Circuit
Open Circuit
-
V
DD
-0.05
-
0.7V
DD
0.05
-
0.3V
DD
-
-
-
-
V
DC
V
DC
V
DC
V
DC
mA
mA
mA
V
OH
= 4.6V, V
DD
= 5V
V
OH
= 4.6V, V
DD
= 5V
V
OH
= 0.4V, V
DD
= 5V
-0.12
-0.04
0.36
DIFFERENTIAL TRANSCEIVER (SEE FIGURE 4) TRANSMITTER
BUS+
I
AOL
I
AOH
BUS-
I
BOL
I
BOH
I
AOL
- I
BOL
Match
Output Rise Time (BUS+)
Output Fall Time (BUS-)
Transition match (50% Point)
RECEIVER
Differential Sensitivity
V
IDH
V
IDL
Hysteresis (Within V
IDH
, V
IDL
Limits)
Propagation Delay
Out of Range
V
H
t
P
V
AX
V
MIN
Quiescent Device Current
Clock Speed
I
DD
f
OP
V
O
= 2.5V, R
L
= 120Ω, V
DD
= 5V
V
O
= 2.5V, R
L
= 120Ω, V
DD
= 5V
V
O
= 2.5V, R
L
= 120Ω, V
DD
= 5V
V
IDH
=120mV, V
DD
= 5V
V
DD
= 5V
V
DD
= 5V
V
DD
= 0V, V
O
= 2.5V
V
DD
= 5, R
L
= 120Ω, C
L
= 25pF
-
20
20
-
3.8
-
-10
-
120
-
-
700
-
1.2
10
TBD
(Note)
mV
mV
mV
ns
V
V
µA
MHz
I
M
t
R
t
F
t
M
V
O
= V
DD
/2, R
L
= 120Ω
V
O
= V
DD
/2, R
L
= 120Ω
V
O
= V
DD
/2, R
L
= 120Ω
V
O
= V
DD
/2, R
L
= 120Ω
V
O
= V
DD
/2, R
L
= 120Ω,
V
DD
= 5V
±0.5V
V
DD
= 5V, C
L
= 25pF
V
DD
= 5V, C
L
= 25pF
V
DD
= 5V, C
L
= 25pF
2.75
-1.0
-
-1.0
-
-
-
-50
-
1.0
-2.75
1.0
5
1.5
1.5
50
mA
µA
mA
µA
%
µs
µs
ns
NOTE: Although 1MHz is generally used as an example throughout this datasheet, the maximum speed limit may be higher and depends
upon user’s noise tolerance requirements.
6-86
CDP68HC68S1
The Serial Bus IC offers the user three possible modes of
operation as defined by Table 1 - SCl (Note 1), SPl, and Buff-
ered SPl. Also included is a “three-state mode” entered by
pulling the CS pin high while in the Buffered SPI mode. As
the name implies, the SCl mode is used when communicat-
ing through the microcomputer’s SCl port. In this mode,
asynchronous NRZ data format (1 start bit, 8 data bits ‘least
significant bit first’, and 1 stop bit) and baud rate remain the
same on each “side” of the SBlC, i.e. to and from the micro
and to and from the differential network bus.
TABLE 1. MODE AND CHIP SELECT DEFINITION
SBI CHIP MODE
SCI
SPI
Buffered SPI
Three-State (Note 2)
NOTES:
1. SCI is the UART interface of a 68HCO5 MCU. The
CDP68HC68S1 is compatable with most UART devices.
2. The three-state mode is only entered when using the Buffered
SPI mode. In the three-state mode, only the XMIT, REC, and
SCK pins are three-stated. The CONTROL and IDLE pins are al-
ways active.
MODE PIN
1
1
0
0
CS PIN
1
0
0
1
bus “monitoring”. The Serial BUS Interface chip handles bus
arbitration, data collision detection, and provides short circuit
protection.
A 68HC0S MCU’s SPI port may instead be used for bus
communication. Two modes of SPl operation are available
with the SBIC - one essentially places the 68HC05 micro-
computer in the slave mode and the other allows the MCU to
remain a master. In the normal SPl mode the SBIC acts as a
master and supplies a data-synchronizing serial clock signal
to the micro (which operates in the slave mode) for shifting
data in or out of the micro’s 8-bit SPl data register. Again,
baud rates are the same on each side of the SBlC, however,
the user must reverse the bit order of a byte transmitted or
received via the SPI port due to the SPl’s most significant bit
first serial data nature. In addition, since the user microcom-
puter is operating in the slave mode it must signal the SBI
chip (by pulling the CONTROL line low) to initiate a transmis-
sion. As in the SCl mode, during a transmission, the byte
originally in the SPI data register is replaced by the byte
reflected from the bus.
Transmission and reception of data in the Buffered SPI mode
allows the user to free the micro’s SPl port by allowing fast
data communication (1M bits/second) between the SPI port
and SBlC. For instance, if the MCU is transmitting, the SBlC
converts the data stream from the MCU’s SPl port to a
slower speed for transmission along the differential bus
when the bus becomes idle. Data speed conversion is
accomplished via a 2 byte (16-bit) data buffer register resid-
ing in the serial bus chip. In this mode the MCU operates as
a master and provides the serial clock signal to the slave
SBlC peripheral. After fast data has been sent to or received
from the SBIC, the micro can pull the SBlC’s CS pin high
(placing the SBlC chip in the three-state mode) and then use
the SPl port to access other SPl peripherals.
All transfers between the user MCU and the SBlC in the
Buffered SPI mode consist of 2 bytes, i.e. a message con-
sists an even number of 8-bit transfers. A microcomputer
wishing to transmit loads 2 bytes into the serial bus IC data
register and then pulls the control pin low to initiate transmis-
sion. During transmission the 2 bytes placed into the buffer
are replaced by the two reflected bytes received from the
bus. After every 2 byte transmission the user micro should
transfer the two reflected bytes out of the buffer and the next
2 bytes to be transmitted into the buffer.
TABLE 2. CLOCK PROGRAMMING
During data transmission, while a byte is being transmitted
from the MCU through the SBl chip onto the differential bus,
it is also reflected and simultaneously received back at the
micro, (this is required for bus arbitration as described later).
DIFFERENTIAL BUS
SBI
SBI
SBI
SPI OR SCI
SPI OR SCI
SPI OR SCI
CLOCK INPUT
DIVIDE FACTOR
A PIN
0
0
1
1
B PIN
0
1
0
1
MCU
MCU
MCU
÷
1
÷
2
FIGURE 1. POSSIBLE NETWORK CONFIGURATION-VARIOUS
MICROCOMPUTERS USING SBI CHIPS TO COM-
MUNICATE ALONG DIFFERENTIAL BUS.
÷
4
÷
10
In addition to performing a framing error check in the SCI
mode, other advantages gained by using the SBlC (in any
mode) include greater system EMl tolerance and automatic
6-87
CDP68HC68S1
Functional Pin Description
PIN NUMBER
1
SYMBOL
CLK
IN/OUT
Input
DESCRIPTION
This is the clock input that shall be divided by the SBIC (as described in Table 2) and used
as an internal synchronizing clock. The internal clock is then further divided by 128 to de-
termine baud rate, i.e. 128 internal clock periods constitute 1-bit length.
Programing inputs of the clock divider. These inputs are tied to +V
DD
or V
SS
depending
upon speed of external clock source. (See Table 2)
This input shall be used in conjunction with CS input to define the mode of operation (see
Table 1). It may be permanently wired to +V
DD
or V
SS
or driven high or low by MCU I/O
lines.
This is the two wire differential bus I/O used to transmit and receive data to and from the
differential bus. BUS+ is both responsive to, or driven positive by sourcing current from
an externally established bias point. This sourcing current matches the BUS- I/Os sinking
current. BUS- is both responsive to, or driven negative by sinking current from an exter-
nally established bias point. This sinking current matches the BUS+ I/Os sourcing current.
Power and ground reference are supplied to the device via these pins. V
DD
is power and
V
SS
is ground.
In the SCI mode this data input shall come from the microcomputer standard NRZ asyn-
chronous communications output port (68HC05 SCI port pin TxD). In the SPI modes, it
shall come from the microcomputer’s synchronous output port (68HC05 SPI port pin
MOSl or MlSO).
In the SCI mode this data output shall be fed into the microcomputer asynchronous com-
munications input port (68HC05 SCI port pin RxD). In the SPI modes it shall be fed into
the microcomputer’s synchronous input port (6805 SP1 port pin MOSl or MISO).
In the SCI mode, this I/O is not required. In both SPI modes this pin is connected to the
68HC05’s SPI port SCK pin. In the normal SPl mode, the SBlC shall produce shift clock
pulses via this pin for synchronously shifting data into and out of the microcomputer. In
the Buffered SPl mode this pin is an input and the microcomputer shall generate the shift
clock pulses. Figure 3 shows the relationship between the serial clock signal and other
SBIC signals in the SPI mode.
This input shall be used in conjunction with the mode input and shall be used as a chip
select (see Table 1). It may be permanently wired to +V
DD
or V
SS
or driven high or low by
MCU I/O lines.
The microcomputer shall monitor this signal to determine the bus condition and also pull
this line low to generate a break. The IDLE signal goes low when the bus is idle (after
sensing an End of Message condition) and high when the bus is active. On reset, this pin
is set to a logic zero.
The microcomputer shall monitor this I/O pin in the SPl mode to handle transmission and
reception of data. In the SCI and SPI modes, as an output, this pin will go low to indicate
that a data byte is currently active on the bus. In the Buffered SPI mode the control pin
indicates whether the user microcomputer has current access to the SBI chip’s internal 2
byte buffer (signified by a logic high on the control pin). In both SPI modes the control pin
is also effective as an input. In these modes the control pin is pulled low by the user mi-
crocomputer to initiate a transmit operation by the SBlC. The control pin is normally high
when the bus is inactive. On reset, this pin is set to a logic high.
2, 3
A and B
Input
4
Mode
Input
5, 6
BUS+
and BUS-
Input/Output
14, 7
V
DD
and
V
SS
XMIT
-
8
Input
9
REC
Output
10
SCK
Input/Output
11
CS
Input
12
IDLE
Input/Output
13
Control
Input/Output
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
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