The XRD8775 is an 8-bit Analog-to-Digital Converter in
a small 20-pin SOIC/SSOP package. Designed using
an advanced 5V CMOS process, this part offers excel-
lent performance, low power consumption and latch-up
free operation.
This device uses a two-step flash architecture to
maintain low power consumption at high conversion
rates. The input circuitry of the XRD8775 includes an
on-chip S/H function and allows the user to digitize
analog input signals between AGND and AV
DD
. Careful
design and chip layout have achieved a low analog input
capacitance. This reduces “kickback” and eases the
requirements of the buffer/amplifier used to drive the
XRD8775.
The designer can choose the internally generated
reference voltages by connecting V
RB
to V
RBS
and V
RT
to
V
RTS
, or provide external reference voltages to the V
RB
and V
RT
pins. The internal reference generates 0.6V at
V
RB
and 2.6V at V
RT
. Providing external reference
voltages allows easy interface to any input signal range
between GND and V
DD
. This also allows the system to
adjust these voltages to cancel zero scale and full
scale errors, or to change the input range as needed.
The device operates from a single +5V supply. Power
consumption is 75mW at F
S
= 15MHz.
Specified for operation over the commercial / industrial
(-40 to +85°C) temperature range, the XRD8775 is
available in Surface Mount (SOIC), Shrink Small Out-
line (SSOP) and Plastic Dual-In-line (PDIP) Packages.
SIMPLIFIED BLOCK AND TIMING DIAGRAM
Rev. 4.00
EXAR
Corporation, 48720 Kato Road, Fremont, CA 94538
•
(510) 668-7000
•
FAX (510) 668-7017
XRD8775
ORDERING INFORMATION
Package
Type
SOIC
PDIP
SSOP
Temperature
Range
-40 to +85°C
-40 to +85°C
-40 to +85°C
DNL
(LSB)
+/-0.75
+/-0.75
+/-0.75
INL
(LSB)
+/-1.5
+/-1.5
+/-1.5
Part No.
XRD8775AID
XRD8775AIP
XRD8775AIU
PIN CONFIGURATIONS
See Packaging Section for Package Dimensions
20-Pin PDIP (300 MIL) - P20
20-Pin SOIC (Jedec, 300 MIL) - D20
20-Pin SSOP (5.3mm) - U20
PIN OUT DEFINITIONS
PIN NO.
1
2
3
4
5
6
7
8
9
10
NAME
DGND
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DV
DD
DESCRIPTION
Digital Ground
Data Output Bit 0 (LSB)
Data Output Bit 1
Data Output Bit 2
Data Output Bit 3
Data Output Bit 4
Data Output Bit 5
Data Output Bit 6
Data Output Bit 7 (MSB)
Digital Power Supply
PIN NO.
11
12
13
14
15
16
17
18
19
20
NAME
CLK
DV
DD
V
RTS
V
RT
AV
DD
V
IN
AGND
V
RBS
V
RB
DGND
DESCRIPTION
Sample Clock
Digital Power Supply
Generates 2.6V if tied to V
RT
Top Reference
Analog Power Supply
Analog Input
Analog Ground
Generates 0.6V if tied to V
RB
Bottom Reference
Digital Ground
Rev. 4.00
2
XRD8775
ELECTRICAL CHARACTERISTICS TABLE
UNLESS OTHERWISE SPECIFIED: AV
DD
= DV
DD
= 5V, FS = 15MHZ (50% DUTY CYCLE),
V
RT
= 2.6V, V
RB
= 0.6V, T
A
= 25°C
25°C
Parameter
KEY FEATURES
Resolution
Sampling Rate
ACCURACY
Differential Non-Linearity
Differential Non-Linearity
Integral Non-Linearity
Zero Scale Error
Full Scale Error
REFERENCE VOLTAGES
Positive Ref. Voltage
Negative Ref. Voltage
Differential Ref. Voltage
3
Ladder Resistance
Ladder Temp. Coefficient
Self Bias 1
Short V
RB
and V
RBS
Short V
RT
and V
RTS
Self Bias 2
V
RB
= AGND,
Short V
RT
and V
RTS
ANALOG INPUT
Input Bandwidth (–1 dB)
2, 4
Input Voltage Range
Input Capacitance
Aperture Delay
2
5
Symbol
Min
8
Typ
Max
Units
Bits
Test Conditions/Comments
FS
DNL
DNL
INL
EZS
EFS
V
RT
V
RB
V
REF
R
L
R
TCO
V
RB
V
RT
-V
RB
V
RT
0.1
15
20
+/-0.75
MHz
LSB
LSB
LSB
LSB
LSB
@ 15MHz
@ 10MHz
Best Fit Line
(Max INL – Min INL)/2
+/-0.5
+/-1.5
+3
-2
2.6
AGND
1.0
245
350
2000
0.6
2
2.3
0.6
AV
DD
550
AV
DD
V
V
V
V
REF
= V
RT
– V
RB
Ω
ppm/°C
V
V
V
BW
V
IN
C
IN
t
AP
V
IH
V
IL
4.0
V
RB
50
V
RT
16
3
MHz
V
pF
ns
V
1.0
V
V
IN
=DGND to DV
DD
DIGITAL INPUTS
Logical “1” Voltage
Logical “0” Voltage
DC Leakage Current
CLK
Input Capacitance
Clock Timing
(
See Figure 1.)
Clock Period
High Pulse Width
Low Pulse Width
DIGITAL OUTPUTS
Logical “1” Voltage
Logical “0” Voltage
Data Valid Delay
8
7
6
I
IN
5
5
1/FS
t
PWH
t
PWL
V
OH
V
OL
t
DL
10
50
25
25
4.5
0.4
66.7
33.3
33.3
µ
A
pF
ns
ns
ns
C
OUT
=15 pF
V
V
ns
I
LOAD
= 4 mA
I
LOAD
= 4 mA
Rev. 4.00
3
XRD8775
ELECTRICAL CHARACTERISTICS TABLE (CONT'D)
UNLESS OTHERWISE SPECIFIED: AV
DD
= DV
DD
= 5V, FS = 15MHZ (50% DUTY CYCLE),
V
RT
= 2.6V, V
RB
= 0.6V, T
A
= 25°C
25°C
Parameter
AC PARAMETERS
Differential Gain Error
Differential Phase Error
POWER SUPPLIES
Operating Voltage (AV
DD
, DV
DD
)
9
Current (AGND + DGND)
V
DD
I
DD
4.5
5
15
5.5
25
V
mA
Does not include ref. current
d
G
d
PH
2
1
%
Degree
FS = 4 x NTSC
FS = 4 x NTSC
Symbol
Min
Typ
Max
Units
Test Conditions/Comments
NOTES
1. The difference between the measured and the ideal code width (V
REF
/256) is the DNL error (Figure 3). The INL error is the maximum distance (in LSBs) from the best fit line to any transition
voltage (Figure 4). Accuracy is a function of the sampling rate (FS).
2. Guaranteed, not tested.
3. Specified values guarantee functionality. Refer to other parameters for accuracy.
4. –1dB bandwidth is a measure of performance of the A/D input stage (S/H + amplifier). Refer to other parameters for accuracy within the specified bandwidth.
5. See V
IN
input equivalent circuit (Figure 5). Switched capacitor analog input requires driver with low output resistance.
6. All inputs have diodes to DV
DD
and DGND. Input DC currents will not exceed specified limits for any input voltage between DGND and DV
DD
.
7. t
R
, t
F
should be limited to >5ns for best results.
8. Depends on the RC load connected to the output pin.
9. AGND & DGND pins are connected through the silicon substrate. Connect together at the package and to the analog ground plane.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS (
T
A
= +25
°
C unless otherwise noted)
1, 2, 3
V
DD
to GND .......................................................... 7V
V
RT
& V RB ......................... V
DD
+0.5 to GND –0.5V
V
IN
..................................... V
DD
+0.5 to GND –0.5V
All Inputs ............................ V
DD
+0.5 to GND –0.5V
All Outputs ......................... V
DD
+0.5 to GND –0.5V
Storage Temperature .........................–65 to +150°C
Lead Temperature (Soldering 10 seconds) ... +300°C
1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification
is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
2. Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection
diodes which will protect the device from short transients outside the supplies of less than 100µA for less than 100ms.
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