590AD-BDG datasheet, PDF - EEWORLD Datasheet

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590AD-BDG: Descriptionosc prog 3.3V lvpecl high 7ppm; CategoryPassive components; File Size115KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

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osc prog 3.3V lvpecl high 7ppm

590AD-BDG Parametric

Parameter Name	Attribute value
Datasheets
SI590/591
Product Photos
Si590 591 series.jpg
Product Training Modules
Crystal Oscillators and Voltage Controlled Oscillators
Clock Tree Timing Solutions
Featured Produc
Si590 and Si591 Low Jitter Xos, Includes Part Order Guide
Standard Package	1
Category	Crystals and Oscillators
Family	Programmable Oscillators
Packaging	Tray
Type	Programmed by Digi-Key (Enter your frequency in Web Order Notes)
Available Frequency Range	125MHz ~ 214.99MHz
Functi	Tri-State (Output Enable)
Outpu	LVPECL
Voltage - Supply	3.3V
Frequency Stability	±7ppm
Operating Temperature	-40°C ~ 85°C
Spread Spectrum Bandwidth	-
Current - Supply (Max)	125mA
Mounting Type	Surface Mou
Package / Case	6-SMD, No Lead (DFN, LCC)
Heigh	0.071" (1.80mm)
Size / Dimensi	0.276" L x 0.197" W (7.00mm x 5.00mm)
Current - Supply (Disable) (Max)	-
Dynamic Catalog	Si590 Series with Ordering Guide

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S i 5 9 0 / 5 91

1 ps M

I T T E R

RYSTAL

SC ILLA TOR

(XO)

(10 M H

Z TO

810 MH

)

Features

Available with any-frequency output



frequencies from 10 to 810 MHz



3rd generation DSPLL

with superior



jitter performance: 1 ps max jitter



Better frequency stability than SAW-



based oscillators



Internal fundamental mode crystal

ensures high reliability



Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

–40 to +85 ºC operating

temperature range

Si5602

Applications



Ordering Information:

See page 7.



SONET/SDH (OC-3/12/48)



Networking



SD/HD SDI/3G SDI video

Test and measurement



Storage



FPGA/ASIC clock generation

Description

The Si590/591 XO utilizes Silicon Laboratories’ advanced DSPLL

circuitry

to provide a low jitter clock at high frequencies. The Si590/591 supports any

frequency from 10 to 810 MHz. Unlike a traditional XO, where a unique

crystal is required for each output frequency, the Si590/591 uses one fixed

crystal to provide a wide range of output frequencies. This IC based

approach allows the crystal resonator to provide exceptional frequency

stability and reliability. In addition, DSPLL clock synthesis provides superior

supply noise rejection, simplifying the task of generating low jitter clocks in

noisy environments typically found in communication systems. The

Si590/591 IC based XO is factory configurable for a wide variety of user

specifications including frequency, supply voltage, output format, and

stability. Specific configurations are factory programmed at time of shipment,

thereby eliminating long lead times associated with custom oscillators.

Pin Assignments:

See page 6.

(Top View)

CLK–

GND

CLK+

Si590 (LVDS/LVPECL/CML)

Functional Block Diagram

CLK– CLK+

GND

CLK

17 k



Any-rate

10–810 MHz

DSPLL

Clock

Synthesis

Si590 (CMOS)

Fixed

Frequency

CLK–

17 k



GND

CLK+

GND

*Note: Output Enable High/Low Options Available – See Ordering Information

Si591 (LVDS/LVPECL/CML)

Rev. 1.0 8/11

Si590/591

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