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PX-721-HDJ-HCAN-40M2830630

Description
LVDS Output Clock Oscillator, 40.283063MHz Nom, ROHS COMPLIANT, HERMETIC SEALED PACKAGE-6
CategoryPassive components    oscillator   
File Size620KB,9 Pages
ManufacturerVectron International, Inc.
Websitehttp://www.vectron.com/
Environmental Compliance  
Download Datasheet Parametric View All

PX-721-HDJ-HCAN-40M2830630 Overview

LVDS Output Clock Oscillator, 40.283063MHz Nom, ROHS COMPLIANT, HERMETIC SEALED PACKAGE-6

PX-721-HDJ-HCAN-40M2830630 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Objectid1262858655
package instructionROHS COMPLIANT, HERMETIC SEALED PACKAGE-6
Reach Compliance Codecompliant
Other featuresENABLE/DISABLE FUNCTION; COMPLEMENTARY OUTPUT; TR, 7 INCH
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability32%
JESD-609 codee4
Installation featuresSURFACE MOUNT
Nominal operating frequency40.283063 MHz
Maximum operating temperature70 °C
Minimum operating temperature-20 °C
Oscillator typeLVDS
physical size7.0mm x 5.0mm x 1.62mm
longest rise time0.35 ns
Maximum supply voltage2.75 V
Minimum supply voltage2.25 V
Nominal supply voltage2.5 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceGold (Au) - with Nickel (Ni) barrier
PX-721
Single Frequency HPLL XO
PX-721
Descrip on
The PX-721 is a crystal oscillator, XO, based upon Vectron’s HPLL high performance phase locked loop frequency mul plier ASIC, that combines
key digital synthesis techniques with VI’s proven core analog technology blocks. A standard low frequency crystal provides the reference to
the frac onal-n synthesizer so that virtually any frequency between 10MHz and 1200 MHz can be factory programmed allowing quick turn
manufacturing.
Features
Applica ons
Features
• Industry Standard Package, 5.0 x 7.0 x 1.8 mm
• HPLL High Performance PLL ASIC
• Ji er < 500 fs-rms (12 kHz to 20 MHz)
• Output Frequencies from 10 MHz to 1200 MHz
• Spurious Suppression, 70 dBc Typical
• 2.5V or 3.3V Supply Voltage
• LVCMOS, LVPECL or LVDS Output Configura ons
• Output Enable
• Compliant to EC RoHS Direc ve
Applica ons
PLL circuits for clock smoothing and frequency transla on
Descrip on
Standard
• 1-2-4 Gigabit Fibre Channel
• 10 Gigabit Fibre Channel
• 10GbE LAN / WAN
• Synchronous Ethernet
• OC-192
• SONET / SDH
INCITS 352-2002
INCITS 364-2003
IEEE 802.3ae
ITU-T G.8262
ITU-T G.709
GR-253-CORE Issue4
Block Diagram
V
DD
COutput
Output
XTAL
LVCMOS
LVPECL
LVDS
HPLL
OE or NC
OE or NC
Gnd
Figure 1 - Block Diagram
Page 1 of 9
Vectron Interna onal • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • h p://www.vectron.com
Rev2: 14 November 2012
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