Typical specifications represent average readings at 25°C and V
DD
= 5 V.
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
V
AB
= V
DD
, Wiper (V
W
) = no connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V
A
= V
DD
and V
B
= 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
The A, B, and W resistor terminals have no limitations on polarity with respect to each other.
6
Guaranteed by design; not subject to production test.
7
The minimum voltage requirement on the V
IH
is 0.7 V × V
DD
. For example, V
IH
minimum = 3.5 V when V
DD
= 5 V. It is typical for the SCL and SDA resistors to be pulled up
to V
DD
. However, care must be taken to ensure that the minimum V
IH
is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-
up resistors.
8
Guaranteed by design; not subject to production test.
9
Different from operating power supply; power supply for OTP is used one time only.
10
Different from operating current; supply current for OTP lasts approximately 400 ms for one-time need only.
11
See Figure 24 for the energy plot during the OTP program.
12
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
13
Bandwidth, noise, and settling time depend on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
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