EEWORLDEEWORLDEEWORLD

Part Number

Search

5962-01-251-7068

Description
EE PLD, 40ns, PAL-Type, TTL, CDIP20
CategoryProgrammable logic devices    Programmable logic   
File Size1MB,25 Pages
ManufacturerAMD
Websitehttp://www.amd.com
Download Datasheet Parametric View All

5962-01-251-7068 Overview

EE PLD, 40ns, PAL-Type, TTL, CDIP20

5962-01-251-7068 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Objectid1157444758
package instructionDIP, DIP20,.3
Reach Compliance Codecompliant
ECCN code3A001.A.2.C
ArchitecturePAL-TYPE
JESD-30 codeR-XDIP-T20
Number of entries16
Output times8
Number of product terms64
Number of terminals20
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output functionCOMBINATORIAL
Package body materialCERAMIC
encapsulated codeDIP
Encapsulate equivalent codeDIP20,.3
Package shapeRECTANGULAR
Package formIN-LINE
power supply5 V
Programmable logic typeEE PLD
propagation delay40 ns
Certification statusNot Qualified
Filter level38535Q/M;38534H;883B
Nominal supply voltage5 V
surface mountNO
technologyTTL
Temperature levelMILITARY
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
The problem of Android emulator's navigation keys not working well
The navigation keys, up, down, left, right and confirmation keys on my Android emulator do not respond. Does anyone know what the problem is? Is it because the version is too high and not supported? I...
chenbingjy Linux and Android
First meeting
I am very happy to share the joy of learning embedded systems with you....
ljm945 Talking about work
Questions about data conversion
[table=98%,rgb(209, 217, 226)] [tr][td] [/td][td]DBH[/td][td]DBL[/td][/tr] [tr][td]Before conversion[/td][td]0 0 0 0 D11 D10 D9 D8[/td][td]D7 D6 D5 D4 D3 D2 D1 D0[/td][/tr] [tr][td]After conversion[/t...
功夫佬 51mcu
FPGA-based SATA controller.doc
FPGA-based SATA controller.doc...
zxopenljx FPGA/CPLD
EDA experiment and practice dac_test
module dac_test(clock,key,wr_act,wr_data,seg,dig); input clock; //system clock (48MHz) input[4:0] key; //key input (KEY1~KEY5) output wr_act; //data enable output[10:0]wr_data; //data to be sent outpu...
白丁 FPGA/CPLD

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2721  875  853  1718  2717  55  18  35  24  56 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号