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I643-33AB8O2-155.520

Description
LVDS Output Clock Oscillator,
CategoryPassive components    oscillator   
File Size119KB,3 Pages
ManufacturerILSI
Websitehttp://www.ilsiamerica.com
Download Datasheet Parametric View All

I643-33AB8O2-155.520 Overview

LVDS Output Clock Oscillator,

I643-33AB8O2-155.520 Parametric

Parameter NameAttribute value
Objectid7019823026
Reach Compliance Codecompliant
Other featuresCOMPLIMENTARY OUTPUT; TR, 7/10 INCH
Maximum control voltage3.3 V
Minimum control voltage
maximum descent time0.8 ns
Frequency Adjustment - MechanicalNO
Frequency offset/pull rate50 ppm
frequency stability25%
linearity10%
Installation featuresSURFACE MOUNT
Nominal operating frequency155.52 MHz
Maximum operating temperature70 °C
Minimum operating temperature-20 °C
Oscillator typeLVDS
Output load100 OHM, 5 pF
physical size3.2mm x 2.5mm x 1.0mm
longest rise time0.8 ns
Maximum supply voltage3.465 V
Minimum supply voltage3.135 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry55/45 %
3.2 mm x 2.5 mm Ceramic Low Noise SMD VCXO
LVCMOS/LVPECL/LVDS
I643 Series
Product Features
Small Surface Mount Package
Fast Sample Delivery
Fast Sample Delivery
Pb Free/ RoHS Compliant
Leadfree Processing
Applications
xDSL
Broadcast Video
Wireless Base Stations
Sonet /SDH
WiMAX/WLAN
Server and Storage
Ethernet/LAN/WAN
Optical modules
Clock and data recovery
FPGA/ASIC
Backplanes
GPON
3.20±0.10
Marking
2.50±0.10
Frequency
LVCMOS
LVPECL
LVDS
Output Level
LVCMOS
LVPECL
LVDS
Duty Cycle
LVCMOS
LVPECL
LVDS
Rise / Fall Time
LVCMOS
LVPECL
LVDS
Output Load
LVCMOS
LVPECL
LVDS
Frequency Stability
Supply Voltage (Vcc)
Aging
Current
10.000MHz to 250.000MHz
10.000MHz to 1500.000MHz
10.000MHz to 1500.000MHz
Logic “0” = 10% of Vcc max., Logic “1” = 90% of Vcc min.
Logic “0”= Vcc-1.62V max., Logic “1” = 1.02 V min
VOD = (Diff. Output) 350mV Typ.
50% ±5% @ 50% of Vcc
50% ±5% @ 50%*
50% ±5% @ 50%*
2.0 ns max. (10% to 90%)*
0.8 ns max. (20% to 80%)*
0.8 ns max. (20% to 80%)*
15pF
50
to Vcc - 2.0 VDC
RL=100
/CL=
5pF
See Table Below
+3.30 VDC ± 5%, +2.50 VDC ± 5%
±3.0 ppm max per year
HCMOS = 45 mA max
LVPECL = 90 mA max
LVDS = 35 mA max
10% max.
See Table Below
1.65 VDC ± 1.65 VDC @ 3.3V
1.25 VDC ± 1.25 VDC @ 2.5V
50K
min.
0.5 ps typical (12kHz to 20MHz)
See Table Below
-40
C to +85
C
.70
.60
TYP
1
2
3
1.00±0.15
1.30
TYP
6
5
4
1.60
2.30
1.80
.90
.80
Suggested Land Pattern
PIN CONNECTIONS
Voltage Control
PIN 1
PIN 2
PIN 3
PIN 4
PIN 5
PIN 6
Enable/Disable
or N/C
Ground
Output
Comp. Output
or N/C
Voltage Supply
.90
Linearity
Pullability
Control Voltage
Input Impedance
Phase Jitter(RMS)
At 12kHz to 20MHz
Operating Temp. Range
Storage Temp. Range
Dimension Units: mm
Part Number Guide
Package
Input
Voltage
3 = 3.3V
6 = 2.5V
Sample Part Number:
Stability
(in ppm)
F =
20
A =
25
B =
50
I643–31AB9H2–155.520
Enable / Disable
(Pin 2)
H = Enable
O = N/C
Operating
Temperature
1 = 0 C to +70 C
2 = -40 C to +85 C
3 = -20 C to +70
C
Pullabilty
B =
50
C =
100
Output
3 = LVCMOS
8 = LVDS
9 = LVPECL
Complimentary
Ouput (Pin 5) **
1 = N.C.
2 = Output
Frequency
I643
-155.520 MHz
NOTE: A 0.01 µF bypass capacitor is recommended between V
DD
(pin 6) and GND (pin 3) to minimize power supply noise. * Measured as percent of
waveform. ** Available on LVDS and LVPECL ouput only
.
ILSI America Phone 775-851-8880
Fax 775-851-8882
●email:
e-mail@ilsiamerica.com
www.ilsiamerica.com
Specifications subject to change without notice
Rev: 03/10/15_A
Page 1 of 3
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