Features ....................................................................................................................................................................................... 1
Ordering Information .................................................................................................................................................................... 2
LVPECL and FlexSwing Termination .................................................................................................................................. 17
LVDS, Supply Voltage: 1.8 V
±5%,
2.5 V ±10%, 3.3 V ±10%, 2.25 V to 3.63 V, 1.71 V to 3.63 V ...................................... 18
HCSL, Supply Voltage: 1.8 V
±5%,
2.5 V ±10%, 3.3 V ±10%, 2.25 V to 3.63 V, 1.71 V to 3.63 V ...................................... 18
Low-power HCSL, Supply Voltage: 1.8 V
±5%,
2.5 V ±10%, 3.3 V ±10%, 2.25 V to 3.63 V, 1.71 V to 3.63 V.................... 18
Dimensions and Patterns ― 2.0 x 1.6 mm x mm ....................................................................................................................... 19
Dimensions and Patterns ― 2.5 x 2.0 mm x mm ....................................................................................................................... 20
Dimensions and Patterns ― 3.2 x 2.0 mm x mm ....................................................................................................................... 21
Revision History ......................................................................................................................................................................... 22
Rev 0.52
Page 3 of 23
www.sitime.com
SiT9375
Low Jitter Differential XO for Standard Frequencies
Electrical Characteristics
ADVANCED
All Min and Max limits in the Electrical Characteristics tables are specified over operating temperature and rated operating
voltage with standard output termination shown in the termination diagrams. Typical values are at 25°C and nominal
supply voltage.
Table 3. Electrical Characteristics – Common to All Output Signaling Types
Parameter
Output Frequency Range
Frequency Stability
Symbol
f
F_stab
–
Min.
Typ.
Max.
Unit
MHz
ppm
Condition
Refer to frequencies listed in
Ordering Information
section.
Inclusive of initial tolerance, operating temperature, rated power
supply voltage, load variation of 15 pF
±
10%, and 10 years
aging at 25°C
Inclusive of initial tolerance, operating temperature, rated power
supply voltage, load variation of 15 pF
±
10%, and first year aging
at 25°C
Ambient temperature of 25°C
Extended commercial, ambient temperature
Industrial, ambient temperature
Ambient temperature
Extended industrial, ambient temperature
Voltage-supply order code “YY”
Voltage-supply order code “XX”
Voltage-supply order code “18”.
Contact SiTime
for 1.5 V
Voltage-supply order code “25”
Voltage-supply order code “33”
Pins 1 and 2 for OE and SE, respectively
Pins 1 and 2 for OE and SE, respectively
Pins 1 and 2 for OE and SE, respectively
See
Figure 5
and
Figure 7
Measured from the time Vdd reaches its rated minimum value
Measured from the time OE pin toggles to enable logic level to
the time clock pins reach 90% of swing. See
Figure 12
Measured from the time OE pin toggles to disable logic level to
the last clock edge. See
Figure 13
12 kHz to 20 MHz offset frequency integration bandwidth,
156.25 MHz
12 kHz to 20 MHz offset frequency range, 156.25 MHz
12 kHz to 20 MHz offset frequency range, 155.52 MHz
156.25 MHz
156.25 MHz
Frequency Range
Standard frequencies
–
±20
Frequency Stability
–
–
–
10 Year Aging
Operating Temperature Range
F_10y
T_use
–
-20
-40
-40
-40
Supply Voltage
Vdd
1.71
2.25
1.71
2.25
2.97
Input Voltage High
Input Voltage Low
Input Pull-up Impedance
Duty Cycle
Startup Time
Output Enable Time
Output Disable Time
VIH
VIL
Z_in
DC
T_start
T_oe
T_od
70%
–
–
45
–
–
–
–
–
–
±1
–
–
–
–
–
–
1.80
2.50
3.30
–
–
100
–
1
–
–
±25
±30
±50
–
+70
+85
+95
+105
ppm
ppm
ppm
ppm
°C
°C
°C
°C
V
V
V
V
V
Temperature Range
Supply Voltage
3.63
3.63
1.89
2.75
3.63
Input Characteristics
–
Vdd
30%
–
55
5
100+3 clock
cycles
100+3 clock
cycles
Vdd
kΩ
%
ms
ns
ns
Output Characteristics
Startup, OE and SE Timing
Jitter and Phase Noise
RMS Phase Jitter (random)
Spurious Phase Noise
RMS Period
Jitter
[1]
Jitter
[1]
T_phj
PN_spur_a
PN_spur_b
T_jitt_per
T_jitt_cc
Peak Cycle-to-cycle
–
–
–
–
–
200
-110
-80
1
6
–
–
–
–
–
fs
dBc
dBc
ps
ps
Note:
1. Measured according to JESD65B.
Rev 0.52
Page 4 of 23
www.sitime.com
SiT9375
Low Jitter Differential XO for Standard Frequencies
ADVANCED
Table 4. Electrical Characteristics – LVPECL
|
Supply voltages: 2.5 V
±10%,
3.3 V
±10%,
2.25 V to 3.63 V
Parameter
Current Consumption, Output
Enabled without Termination
Current Consumption, Output
Enabled with Termination 1
Current Consumption, Output
Enabled with Termination 2
Current Consumption, Output
Disabled without Termination
Current Consumption Output
Disabled with Termination 1
Current Consumption, Output
Disabled with Termination 2
OE Leakage Current
Symbol
Idd_oe_nt
Idd_oe_wt1
Idd_oe_wt2
Idd_od_nt
Idd_od_wt1
Idd_od_wt2
I_leak
Min.
–
–
–
–
–
–
–
Typ.
43
52
71
58
58
86
37
Max.
–
–
–
–
–
–
–
Unit
mA
mA
mA
mA
mA
mA
mA
Condition
Excluding load termination current
Including load termination current. See
Figure 15
for
termination
Including load termination current. See
Figure 18
for
termination
Excluding load termination current
Including load termination current. See
Figure 15
for
termination
Including load termination current. See
Figure 18
for
termination
OE = disable logic, DC termination, OUTP and OUTN held
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FPGA/CPLD
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