5962-8946302YC datasheet, PDF - EEWORLD Datasheet

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5962-8946302YC: DescriptionMath Coprocessor, 32-Bit, CMOS, CQFP68, CERAMIC, QFP-68; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，43 Pages; Manufacturere2v technologies

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5962-8946302YC Overview

Math Coprocessor, 32-Bit, CMOS, CQFP68, CERAMIC, QFP-68

5962-8946302YC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	QFP
package instruction	QFP, QFP68,1.1SQ,50
Contacts	68
Reach Compliance Code	unknow
ECCN code	3A001.A.2.C
Address bus width	5
boundary scan	NO
maximum clock frequency	20 MHz
External data bus width	32
JESD-30 code	S-CQFP-G68
JESD-609 code	e4
length	24.13 mm
Number of terminals	68
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QFP
Encapsulate equivalent code	QFP68,1.1SQ,50
Package shape	SQUARE
Package form	FLATPACK
power supply	5 V
Certification status	Qualified
Filter level	MIL-STD-883
Maximum seat height	3.43 mm
Maximum slew rate	150 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	GOLD
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	QUAD
width	24.13 mm
uPs/uCs/peripheral integrated circuit type	MATH PROCESSOR, COPROCESSOR
Base Number Matches	1

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TS68882

CMOS Enhanced Floating-point Co-processor

Datasheet

Features

•

Eight General-purpose Floating-point Data Registers, Each Supporting a Full 80-bit Extended Precision Real Data Format (a

•

64-bit Mantissa Plus a Sign Bit, and a 15-bit Signed Exponent)

A 67-bit Arithmetic Unit to Allow Very Fast Calculations with Intermediate are Precision Greater than the Extended Precision

Format

A 67-bit Barrel Shifter for High-speed Shifting Operations (for Normalizing etc.)

Special-purpose Hardware for High-speed Conversion Between Single, Double, and Extended Formats and the Internal

Extended Format

An Independent State Machine to Control Main Processor Communication for Pipelined Instruction Processing

Forty-six Instructions, Including 35 Arithmetic Operations

Full Conformation to the IEEE

754 Standard, Including All Requirements and Suggestions

Support of Functions Not Defined by the IEEE Standard, Including a Full Set of Trigonometric and Transcendental Functions

Seven Data Type Types: Byte, Word and Long Integers; Single, Double, and Extended Precision Real Numbers; and Packed

Binary Coded Decimal String Real Numbers

Twenty-two Constants Available In The On-chip ROM, Including

π,

e, and Powers of 10

Virtual Memory/Machine Operations

Efficient Mechanisms for Procedure Calls, Context Switches, and Interrupt Handling

Fully Concurrent Instruction Execution with the Main Processor

Fully Concurrent Instruction Execution of Multiple Floating-point Instructions

Use with any Host Processor, on an 8-, 16- or 32-bit Data Bus

Available in 16.67, 20, 25 and 33 MHz for T

from -55°C to +125°C

= 5V

10%

Description

The TS68882 enhanced floating-point co-processor is a full implementation of the IEEE Standard for Binary Floating-Point

Arithmetic (754) for use with the THOMSON TS68000 Family of microprocessors. It is a pin and software compatible

upgrade of the TS68881 with optimized MPU interface that provides over 1.5 times the performance of the TS68881. It is

implemented using VLSI technology to give systems designers the highest possible functionality in a physically small

device.

Intended primarily for use as a co-processor to the TS68020/68030 32-bit microprocessor units (MPUs), the TS68882 pro-

vides a logical extension to the main MPU integer data processing capabilities. It does this by providing a very high

performance floating-point arithmetic unit and a set of floating-point data registers that are utilized in a manner that is anal-

ogous to the use of the integer data registers. The TS68882 instruction set is a natural extension of all earlier members of

the TS68000 Family, and supports all of the addressing modes of the host MPU. Due to the flexible bus interface of the

TS68000 Family, the TS68882 can be used with any of the MPU devices of the TS68000 Family, and it may also be used

as a peripheral to non-TS68000 processors.

Visit our website: www.e2v.com

for the latest version of the datasheet

e2v semiconductors SAS 2007

0852B–HIREL–06/07

TS68882

Screening/Quality

This product could be manufactured in full compliance with either:

• MIL-STD-883 Class B

• DESC 5962-89436

or According to e2v-Grenoble Standards

R suffix

PGA 68

Ceramic Pin Grid Array

F suffix

CQFP 68

Ceramic Quad Flat Pack

1. Introduction

The TS68882 is a high-performance floating-point device designed to interface with the TS68020 or

TS68030 as a co-processor. This device fully supports the TS68000 virtual machine architecture, and is

implemented in HCMOS, e2v’s low power, small geometry process. This process allows CMOS and

HMOS (high-density NMOS) gates to be combined on the same device. CMOS structures are used

where speed and low power is required, and HMOS structures are used where minimum silicon area is

desired. The HCMOS technology enables the TS68882 to be very fast while consuming less power than

comparable HMOS, and still have a reasonably small die size.

With some performance degradation, the TS68882 can also be used as a peripheral processor in sys-

tems where the TS68020 or TS68030 is not the main processor (i.e., TS68000, TS68010). The

configuration of the TS68882 as a peripheral processor or co-processor may be completely transparent

to user software (i.e., the same object code may be executed in either configuration).

The architecture of the TS68882 appears to the user as a logical extension of the TS68000 Family archi-

tecture. Coupling of the co-processor interface allows the TS68020/TS68030 programmer to view the

TS68882 registers as though the registers are resident in the TS68020/TS68030. Thus, a TS68020 or

TS68030/TS68882 device pair appears to be one processor that supports seven floating-point and inte-

ger data types, and has eight integer data registers, eight address registers, and eight floating-point data

registers.

As shown in

Figure 1-1,

the TS68882 is internally divided into four processing elements; the Bus Inter-

face Unit (BIU), the Conversion Control Unit (CCU), the Execution Control Unit (ECU), and the

Microcode Control Unit (MCU). The BIU communicates with the main processor, the CCU controls the

main processor communications dialog and performs some data conversions, and the ECU and MCU

execute most floating-point calculations.

The BIU contains the co-processor interface registers, and the 32-bit control, and instruction address

registers. In addition to these registers, the register select and DSACK timing control logic is contained in

the BIU. Finally, the status flags used to monitor the status of communications with the main processor

are contained in the BIU.

0852B–HIREL–06/07

e2v semiconductors SAS 2007

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