CA95C68-25CN datasheet, PDF - EEWORLD Datasheet

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CA95C68-25CN: DescriptionData Encryption Circuit, MOS, PQCC44, PLASTIC, LCC-44; CategoryWireless rf/communication Telecom circuit; File Size180KB，42 Pages; ManufacturerIDT (Integrated Device Technology)

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CA95C68-25CN Overview

Data Encryption Circuit, MOS, PQCC44, PLASTIC, LCC-44

CA95C68-25CN Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Objectid	1460223516
package instruction	PLASTIC, LCC-44
Reach Compliance Code	unknown
JESD-30 code	S-PQCC-J44
JESD-609 code	e0
length	16.4084 mm
Number of functions	1
Number of terminals	44
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC44,.7SQ
Package shape	SQUARE
Package form	CHIP CARRIER
power supply	5 V
Certification status	Not Qualified
Maximum seat height	4.4196 mm
Maximum slew rate	75 mA
Nominal supply voltage	5 V
surface mount	YES
technology	MOS
Telecom integrated circuit types	DATA ENCRYPTION CIRCUIT
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
width	16.4084 mm

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CA95C68/18/09

DES DATA CIPHERING PROCESSORS (DCP)

• Encrypts/Decrypts data using National Bureau

of Standards Data Encryption Standard (DES)

• High speed, pin and function compatible

version of industry standard AMD AM9568,

AM9518 and VLSI VM009

• Supports four standard ciphering modes:

Electronic Code Book (ECB), Cipher Block

Chaining (CBC), as well as 1 and 8 bit Cipher

Feedback (CFB)

• Data rates greater than 11 Mbytes per second

(25 MHz) in ECB or CBC modes

• Three separate registers for encryption,

decryption and master keys improve system

security and throughput by eliminating the need

to reload keys frequently

• Fully static CMOS, TTL I/O compatible device,

operates at up to 33MHz

• Low power consumption allows battery back-up

of internal key registers

• Three separate programmable ports (master,

slave and key data)

• Available in 44 pin PLCC and 40 pin PDIP and 44

pin TQFP packages

3.2

CA95C68/18/09

The

Tundra Semiconductor Corporation

CA95C68/18/09

DES Data Ciphering Processors (DCPs) implement the

National Bureau of Standards Data Encryption Standard

(DES), FIPS PUB 46 (1-15-1977). The DCPs were designed

to be used in a variety of environments where computer and

communications security is essential.

The DCPs provide a high throughput rate (up to 14 Mbytes

per second) using ECB or CBC modes of operation. The

DCPs provide a unique 1 bit CFB mode as well as the

standard 8 bit mode. Separate ports for key input, clear data

and enciphered data enhance security for your application.

The system communicates with the DCP using commands

entered in the Master Port or through auxiliary control lines.

Once the DCP is set up, data can ﬂow through at high speeds

since input, output and ciphering activities are performed

concurrently. External DMA control can easily be used to

enhance throughput in many system conﬁgurations.

The CA95C68 is designed to interface directly to the

iAPX86, 88 CPU bus, and with a minimum of external logic,

to the 2900 and 8051 families of processors. The CA95C18

is designed to interface directly with Z8000, 68000 type bus

interfaces.

The CA95C09 may be conﬁgured to behave as either the

CA95C68 or the CA95C18 (see OPTION pin in Table 3-2),

the only difference being the order of the signal names on

the device package.

Table 3-1 : CA95C68/18/09 Data Transfer Rates

Data Transfer Rates

Product

Code

CA95Cxx – 5

CA95Cxx – 10

CA95Cxx – 16

CA95Cxx – 20

CA95Cxx – 25

CA95Cxx-33

ECB or CBC Mode

(Mbytes/s)

CFB-8 Mode

(Mbytes/s)

CFB-1 Mode

(Mbits/s)

System Clock

(MHz)

2.22

4.44

7.10

8.88

11.11

14.81

0.27

0.55

0.88

1.11

1.38

1.85

0.27

0.55

0.88

1.11

1.38

1.85

Tundra Semiconductor Corporation

3-25

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