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IDT70V3579S6DRI

Description
32K X 36 DUAL-PORT SRAM, 4.2 ns, PQFP208
Categorystorage   
File Size189KB,16 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Download Datasheet Parametric View All

IDT70V3579S6DRI Overview

32K X 36 DUAL-PORT SRAM, 4.2 ns, PQFP208

IDT70V3579S6DRI Parametric

Parameter NameAttribute value
maximum clock frequency133 MHz
Number of functions1
Number of terminals208
Minimum operating temperature0.0 Cel
Maximum operating temperature70 Cel
Rated supply voltage3.3 V
Minimum supply/operating voltage3.15 V
Maximum supply/operating voltage3.45 V
Processing package descriptionPLASTIC, QFP-208
each_compliYes
stateActive
sub_categorySRAMs
ccess_time_max4.2 ns
i_o_typeCOMMON
jesd_30_codeS-PQFP-G208
jesd_609_codee0
storage density1.18E6 bi
Memory IC typeDUAL-PORT SRAM
memory width36
moisture_sensitivity_level3
Number of ports2
Number of digits32768 words
Number of digits32K
operating modeSYNCHRONOUS
organize32KX36
Output characteristics3-STATE
Packaging MaterialsPLASTIC/EPOXY
ckage_codeFQFP
ckage_equivalence_codeQFP208,1.2SQ,20
packaging shapeSQUARE
Package SizeFLATPACK, FINE PITCH
serial parallelPARALLEL
eak_reflow_temperature__cel_225
wer_supplies__v_2.5/3.3,3.3
qualification_statusCOMMERCIAL
seated_height_max4.1 mm
standby_voltage_mi3.15 V
Maximum supply voltage0.4600 Am
surface mountYES
CraftsmanshipCMOS
Temperature levelCOMMERCIAL
terminal coatingTIN LEAD
Terminal formGULL WING
Terminal spacing0.5000 mm
Terminal locationQUAD
ime_peak_reflow_temperature_max__s_20
length28 mm
width28 mm
dditional_featurePIPELINED OUTPUT MODE, SELF-TIMED WRITE CYCLE
HIGH-SPEED 3.3V 32K x 36
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
x
x
IDT70V3579S
x
x
x
x
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 4.2/5/6ns (max.)
– Industrial: 5/6ns (max)
Pipelined output mode
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)
– Fast 4.2ns clock to data out
– 1.8ns setup to clock and 0.7ns hold on all control, data, and
x
x
x
x
x
address inputs @ 133MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
LVTTL- compatible, single 3.3V (±150mV) power supply for
core
LVTTL compatible, selectable 3.3V (±150mV)/2.5V (±125mV)
power supply for I/Os and control signals on each port
Industrial temperature range (-40°C to +85°C) is
available for selected speeds
Available in a 208-pin Plastic Quad Flatpack (PQFP) and
208-pin fine pitch Ball Grid Array, and 256-pin Ball Grid
Array
Functional Block Diagram
BE
3L
BE
3R
BE
2L
BE
1L
BE
0L
BE
2R
BE
1R
BE
0R
R/W
L
B
W
0
L
B
W
1
L
B B
WW
2 3
L L
B
W
3
R
BB
WW
2 1
RR
B
W
0
R
R/W
R
CE
0L
CE
1L
CE
0R
CE
1R
OE
L
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
Dout0-8_R
Dout9-17_R
Dout18-26_R
Dout27-35_R
OE
R
32K x 36
MEMORY
ARRAY
I/O
0L
- I/O
35L
Din_L
Din_R
I/O
0R
- I/O
35R
CLK
L
A
14L
A
0L
CNTRST
L
ADS
L
CNTEN
L
CLK
R
,
Counter/
Address
Reg.
A
14R
ADDR_L
ADDR_R
Counter/
Address
Reg.
A
0R
CNTRST
R
ADS
R
CNTEN
R
4830 tbl 01
JULY 2001
1
©2001 Integrated Device Technology, Inc.
DSC 4830/13
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