EEWORLDEEWORLDEEWORLD

Part Number

Search

D3A2000I17301AFB-G

Description
Parallel - Fundamental Quartz Crystal, 3.2MHz Nom, HC-49/U, 2 PIN
CategoryPassive components    Crystal/resonator   
File Size698KB,3 Pages
ManufacturerDB Lectro Inc
Environmental Compliance  
Download Datasheet Parametric View All

D3A2000I17301AFB-G Overview

Parallel - Fundamental Quartz Crystal, 3.2MHz Nom, HC-49/U, 2 PIN

D3A2000I17301AFB-G Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Objectid1390502800
package instructionHC-49/U, 2 PIN
Reach Compliance Codeunknown
Other featuresAT-CUT; BULK
Ageing3 PPM/YEAR
Crystal/Resonator TypePARALLEL - FUNDAMENTAL
Drive level100 µW
frequency stability0.001%
frequency tolerance30 ppm
load capacitance17 pF
Installation featuresTHROUGH HOLE MOUNT
Nominal operating frequency3.2 MHz
Maximum operating temperature60 °C
Minimum operating temperature-10 °C
physical sizeL11.05XB4.65XH13.46 (mm)/L0.435XB0.183XH0.53 (inch)
Series resistance100 Ω
surface mountNO
QUARTZ CRYSTAL
Holder Code A, RESISTANCE WELDED HC-49/U PACKAGE
FEATURE
Height 13.46mm
A resistance weld completely sealed type
The tight frequency stability
Copes with high density mounting and is the optimum for
mass production
Lead Free & RoHS Compliant
ELECTRICAL SPECIFICATIONS
Nominal frequency:
Oscillation mode:
Operating temperature range
Storage temperature range
Frequency tolerance:
Frequency stability
Load capacitance:
Equivalent series resistance
Parallel capacitance(Co):
Drive level
Insulation resistance:
1.8432MHz to 150.000MHz
See below table
-20℃--+70℃ (Typical), -10℃ ~ +60℃,
-40℃ ~ +85℃, or specify
-40℃--+85℃
±30PPM
at 25±2℃ (Typical), or specify
±50PPM
over -20~70℃ (Typical), or specify
16pF, 18pF, 20pF, 30pF, series, or specify
See below table
7PF Max
100 µW Typical
More than 500MΩ AT DC100V
EQUIVALENT SERIES RESISTANCE(ESR) AND OSCILLATION MODE
Frequency Range
1.843MHz~1.999MHz
2.000MHz~2.399MHz
2.400MHz~2.999MHz
3.000MHz~3.199MHz
3.200MHz~3.499M
Hz
3.500MHz~3.899MHz
3.900MHz~4.099MHz
4.100MHz~5.999MHz
E.S.R
(
Ω)
350Max
300Max
200Max
150Max
100Max
90Max
70Max
60Max
Mode
Fundamental/AT
Fundamental/AT
Fundamental/AT
Fundamental/AT
Fundamental/AT
Fundamental/AT
Fundamental/AT
Fundamental/AT
Frequency Range
6.000MHz~6.999MHz
7.000MHz~9.999MHz
10.000MHz~12.999MHz
13.000MHz~30.000MHz
24.000MHz~29.999MHz
30.000MHz~65.000MHz
60.000MHz~99.999MHz
100.000MHz~150.000MH
z
E.S.R
(
Ω)
50Max
30Max
20Max
20Max
50Max
40Max
90Max
60Max
Mode
Fundamental/
AT
Fundamental/
AT
Fundamental/
AT
Fundamental/
AT
Third
Overtone
Third
Overtone
Third
Overtone
Fundamental/
AT
DB Lectro Inc. 3755 Place Java, Suite 140, Brossard, Québec, J4Y 0E4, Canada - T: 1-450-444-1424 / F: 1-450-444-4714 / www.dblectro.com
Looking for a 40PIN FPC connector package
40 Pin FPC connector, pin spacing is 0.5mm, line spacing is 0.5mm, I need it urgently and don't have time to learn how to draw the package, thank you all for your help!...
面纱如雾 PCB Design
[Challenge] Poor people's MAX7219 7279
In February, I saw a post on the Internet titled "Poor Man's MAX7219 7279". I thought it was good, so I contacted the author and asked if I could share it on our forum. This was the author's reply in ...
soso MCU
Relay interference problem
I am so distressed, please help me, woooo! I recently developed a product that uses relays as on/off devices, but I don't know how to deal with the spark interference caused by turning on the relay! I...
xiaoya Integrated technical exchanges
Mifare card reader development experience
It seems that more and more people in the forum are interested in this. My first card reader was developed using CM200. There is nothing special about the hardware development. CM200 has an internal a...
tmily RF/Wirelessly
Two small questions, scattered ~
1. Use the hardware timer to write a program, set the hour, minute and second timers, the corresponding addresses are: 4000H, 4002H, 4004H, the crystal frequency is 12MHZ (written with 8096) 2.C08__2 ...
zhanqianwen Embedded System
[FPGA entry to actual combat] Xilinx ise development tool generates FIFO ip simulation and timing explanation source code & Q&A
[FPGA entry to actual combat] Xilinx ise development tool generates FIFO ip simulation and timing explanation; Students who do not understand the knowledge points in the video can ask questions in the...
尤老师 FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1424  1698  1588  511  1991  29  35  32  11  41 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号